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Verilab Introduces vzDoc for OpenVera Hardware Verification Language
April 15, 2002  

Verilab Ltd., the United Kingdom-based VLSI verification experts, today announced the availability of an Open VeraTM version of its code documentation tool vzDoc, which provides Javadoc-like functionality for high-level verification languages.

vzDoc improves design team productivity by enabling push-button generation of easy-to-read and understandable on-line HTML reference documentation directly from OpenVera source code. vzDoc uses comments inserted in the source code to generate the online reference documentation. Consequently, vzDoc encourages good commenting and accurate documentation practices, while increasing code readability and design reuse. Integration of the tool into the build and regression environment can also help to ensure consistency with the source code.

"vzDoc avoids the greatest hazard in code documentation--inaccurate comments--because documentation is produced automatically from the code itself, eliminating error-prone duplication of effort", said Jason Sprott, director of Verilab Research and Development. "vzDoc's ease-of-use, combined with OpenVera's sophisticated hardware verification language implementation, significantly reduces the time to create verification testbenches."

The tool parses the declarations and the designer's documented comments in the OpenVera code and produces an XML representation of the hierarchical structure and code elements from which HTML pages are created. This provides a powerful presentation method for code reviews, walk-throughs, reference and training. OpenVera classes, constructors, methods and fields can all be easily documented to a common standard, which makes them more easily shared and reused.

"The OpenVera version of vzDoc is a welcome addition to the growing list of verification solutions available to the OpenVera community," said Jim Watts, OpenVera program manager at Synopsys, Inc. (Nasdaq:SNPS) "OpenVera is an open and non-proprietary hardware verification language available to the entire design community to enable the development of innovative solutions to ease the verification bottleneck."


For more information including how to obtain vzDoc, interested design and verification engineers should visit:

About OpenVera

OpenVera is an open source hardware verification language developed specifically to meet the unique requirements of functional verification. The language enables users to describe the target application environment, including complex protocols and data objects, at a high level of abstraction, which dramatically increases productivity, readability and reusability. The latest OpenVera developments will be featured at the ninth semiannual Synopsys EDA Interoperability Developers' Forum in Sunnyvale, CA on Tuesday, April 16, 2002. For more information on OpenVera and OpenVera verification IP solutions, visit

About Verilab

Verilab Ltd. is a design verification company providing verification methodology, consulting services and training for functional verification of complex system-on-chip (SoC), ASIC and FPGA designs. Founded in 2000, it is privately held. Corporate headquarters is located at Willow House, Strathclyde Business Park, Bellshill, Scotland, ML4 3PB. Telephone: +44 (0) 1698 464500. Facsimile: +44 (0) 1698 464501. Email: Online information can be found on the web at:

vzDoc is a trademark of Verilab Ltd. Javadoc is the tool from Sun Microsystems for generating API documentation in HTML format from doc comments in source code. Synopsys is a registered trademark of Synopsys, Inc. OpenVera is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

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