A guide for knowledgeable SystemVerilog users who need to use Specman and the e language on their job but already have an understanding of constrained-random verification. Looking beyond just the syntax, you will find that there are more similarities than differences between the two languages. Some concepts are unique to the e language, and will be given specific attention. This guide is the culmination of many informal project training and consulting over the past few years.
( Thorsten Dworzak )