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Archive for June, 2015

Thoughts on Verification: svlib - Including the Batteries for SystemVerilog (part 2)

Thursday, June 18th, 2015 by Alex Melikian

In part 2, Alex and Jonathan continue covering features in svlib. In addition, they also cover how someone in the verification community can quickly ramp-up, request support for problems and get involved with svlib. Part 1 can be viewed here.

Alex Melikian: Another feature set offered by svlib in addition to what we’ve talked about so far, would be its functions related to the operating system. Once again, the standard SystemVerilog already offers some functionality interacting with the OS, but svlib takes it a level further. Can you tell us what svlib can do in this respect that SystemVerilog does not?

Jonathan Bromley: I can’t imagine a general-purpose programming language that doesn’t have library or built-in features for figuring out the time of day, discovering the values of environment variables, exploring the filesystem’s directory structure and so forth. We should expect that to be available, without fuss, in SystemVerilog - but, frustratingly, it is not. That’s precisely what svlib’s OS interaction features are intended to offer. There’s a collection of related sets of features - they’re distinct, but in practice you’ll probably use them together.

First, there’s a set of tools (implemented in the Pathname class) that allow you to manipulate Linux file and directory names in a convenient and robust way. If you try to do that as a simple string processing task, you’ll typically get some nasty surprises with things like doubled-up path separators (slashes); the Pathname class copes with all of that. Next, there’s a slew of functions for inquiring about the existence and state of files, mostly based on the “stat” system call that you may be familiar with. You can check whether a file exists, decide if it’s a directory or softlink, find whether you have write permission on it, and examine its creation and modification datestamp. You can also find what files exist at any given location, using the same “glob” syntax (star and query wildcards) that’s familiar to anyone who has used the “ls” command.

Thoughts on Verification: svlib - Including the Batteries for SystemVerilog (part 1)

Wednesday, June 10th, 2015 by Alex Melikian

In this edition of “Thoughts on Verification”, Verilab consultant Alex Melikian interviews colleague Jonathan Bromley, lead author of the svlib library. svlib is a free open source utility functions library for SystemVerilog, available on Verilab’s website.

In part 1, Alex and Jonathan begin the discussion by covering why svlib was created, features it offers, as well as some of the internal details of this open source library.

Alex Melikian: Hi Jonathan! It’s great to have you with us. I believe you’re our first ‘repeat’ interviewee on these ‘Thoughts on Verification’ series, so I should really be saying ‘welcome back’.

Jonathan Bromley: Thanks, Alex! I’m sure you could have found someone more exciting from among our amazing colleagues, but it’s a pleasure to be back in the hot seat.

AM: We’re here to discuss svlib, an ongoing project you’ve been working for some time now. Let’s begin by introducing it for the unfamiliar, how would you best describe svlib?

JB: It’s partly a “pet project” that I’ve been thinking about for some years, and partly a response to genuine needs that I’ve encountered - not only in my own verification work with SystemVerilog, but also when observing what our clients ask for, and what I heard from students back when I was delivering training classes before joining Verilab. It’s a package of general-purpose library functions covering string manipulation, regular-expression processing, file access and operating-system interface stuff such as wall-clock time and directory exploration, and a bunch of other utility functions. Almost all are things that - frustratingly - aren’t available in standard out-of-the-box SystemVerilog, but exist in just about any general-purpose language. With svlib added to your toolkit, SystemVerilog starts to look a lot more like a competent all-round programming language.

Most of the non-trivial functionality in svlib is implemented using SystemVerilog’s fantastic C-language interfaces, the DPI and VPI. For many years, folk who are expert in both SystemVerilog and C/C++ have used those interfaces to implement their own additional functionality. The contribution of svlib, I hope, is to make a wide range of useful new features freely accessible to anyone who’s familiar with SystemVerilog. No C or DPI expertise is needed to use it.


Verilab at 52nd DAC

Thursday, June 4th, 2015 by Paul Marriott

Verilab’s CTO, Jason Sprott will be giving a presentation co-authored with Cadence’s John Brennan entitled Predicting Verification Closure of IP Designs.

Jason will be in Room 101 at 52nd DAC next Tuesday June 9th presenting about how verification closure of IP designs can be both predictable and deterministic. Harnessing the power of big data, a prediction engine will be described which allows metadata from previous projects to be used to forecast all the key metrics for the current project.

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