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Archive for September, 2012

Thoughts on Verification: A ‘Fresh’ Look at UVM (part 1 of 2)

Thursday, September 27th, 2012 by Alex Melikian

The subject of this edition of “Thoughts on Verification” is the UVM, or the Universal Verification Methodology. Verilab consultants Alex Melikian and Vanessa Cooper discuss, explain and give insight to their experiences with the UVM. Before learning UVM, Vanessa had no previous experience with verification methodology. Hence, her opinions provide a ‘fresh’ point of view on the UVM, and what it can offer to the verification community.

In Part 1, Alex gives a brief historical summary on the UVM and its past predecessors. Vanessa talks about her experiences learning and adopting the UVM, having no prior experience with employing any verification methodology library. Alex and Vanessa also discuss UVM’s pros and cons from their respective experiences with it.

Alex Melikian: Hi Vanessa.  Thanks for joining me on this conversation.

Vanessa Cooper: Hi Alex.  How are you today?

AM: I’m doing fine, thank you.  So we’re here today to have a conversation about the UVM, the verification methodology widely pushed by the EDA industry. Not only is it available in SystemVerilog but also for Specman/e.  And before we get into it and your experiences with learning and using UVM, perhaps I should talk about its history for readers who are not familiar with it.

Well, firstly UVM is a verification methodology library standard, where open source code libraries are available as reference implementation.  The available libraries are under the Apache license, but in practical terms it is free. It is not a commercial product, nor an EDA tool.  It’s straight out code that is either based in SystemVerilog or Specman e, but its intent is to be used as a Universal Verification Methodology.  That’s what UVM stands for. Where it came about is from a lineage of previous verification methodologies from different EDA vendors.

If we stay in the SystemVerilog world, the first verification methodologies that came out were AVM and VMM. This was back around 2005-2006. The problem however was that these verification methodologies were tied to their vendors, even though in the case of AVM, which was open source. Of course, it should be mentioned that Specman had the eRM, which was released around 2003, when Verisity was an independent EDA vendor. I mention the eRM because many of its concepts were transposed into the UVM. Back to the SystemVerilog world, after AVM and VMM, OVM came along in 2008. OVM was an evolution of Mentor’s AVM with concepts from Cadence’s URM SystemVerilog methodology. VMM continued on its own evolving path. So again, OVM was not quite universal. OVM was supported and available on some of the major simulators, but not all of them.


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