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Keeping It Real At CDNLive!

I just saw the announcement for CDNLive! Silicon Valley, to be held September 10-12 in San Jose. I’d encourage you to attend. I had the opportunity to attend CDNLive! Europe in May and found it refreshing for a regional vendor-led conference to pack so much good material, interesting people and effective knowledge sharing into 3 days. There were over 550 attendees. The venue was great and the tone was appropriately ‘real’ for a developers’ conference.

As my interest is in verification it was good to hear about the advances in ESL, co-simulation, and SystemVerilog adoption from a Cadence vendor, associate, and user point of view. I also enjoyed hearing the reactions, comments and questions from the industry audience to those topics.

I was there representing Verilab as we are partners with Cadence in the Verification Alliance. Verilab is one of a handful of consulting companies qualified in Cadence’s Incisive Plan-to-Closure Methodology with a presence in both Europe and the US. It was good to meet with Cadence CEO Mike Fister and hear his take on the value proposition of the verification EDA market - it’s an important segment for them - and being qualified in IPCM and uRM is important for us as we in turn help our customers use those methodologies and standards. Plan-to-closure is really all about closure, so it is a good methodology to follow. Cadence frequently references Stephen “7 habits” Covey by instructing teams to “begin with the end in mind”. That’s definitely good advice!

During the 2 days of the main conference there were interesting, relevant and insightful keynotes from Mike Fister, Cadence CEO and René Penning de Vries, NXP Semi CTO. Both emphasised the importance of first-time-right via effective verification. In the Verification track there was a presentation from Giles Hall. Giles demonstrated the Incisive Software Extensions, including a set of features added to VCS Incisive which allow simulation in parallel with debug of the software running on the CPU core in the design, and a methodology for coverage-driven HW/SW co-simulation with HW/SW scenarios put together from a wizard. There were also papers from (among others) Freescale Munich and IBM Stuttgart. The Freescale team are involved in a joint venture with ST and are taking their first steps to migrate to SystemVerilog testbench. IBM Stuttgart is using Specman (with extra rigour) in the Cell processor family verification alongside their home-grown simulator.

The Designer Expo was interesting and well attended, and I spent much of my time there on the Verification Alliance booth talking to many attendees. I should say thanks to all of you who came up and talked and offered their insight into verification, their needs as customers, and Cadence’s solutions. There was a lot of energy in the room throughout the conference. It was also good to see the musical side of Cadence CTO Ted Vucurevich and colleagues, in what was a very professional and entertaining evening event. All in all it was a well organized and worthwhile conference from both a learning and networking point of view.

At San Jose in five weeks time, there are two Functional Verification tracks over the three days, which look to be packed with interesting topics. If you get the chance to attend do let us know what you thought.

2 Responses to “Keeping It Real At CDNLive!”

  1. Teng-Kiat Lee Says:

    Do you really mean VCS?


  2. Gordon Allan Says:

    Yes, thanks for the correction, Teng-Kiat! Too many TLAs in my head. I believe the correct one in this case is ‘IES’.

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