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Verilab at DVCon 2021

February 25, 2021 by Alex Melikian

This year DVCon will be a little different as the conference is going to be fully virtual. However, Verilab’s proud tradition of participating with quality presentations and attendance goes unchanged. We have prepared two presentations for this year’s conference, both streamed live on March 2nd, from DVCon’s website dvcon.org

Our first presentation is “To Infinity and Beyond – Streaming Data Sequences in UVM” from multi-award wining consultants Mark Litterick, Jeff Montesano and Jeff Vance. The presentation will focus on the concept of autonomous stimulus generation using streaming data techniques and discusses its applications in the verification of complex sensor style devices.

Our second will be “Configuration Conundrum: Managing Test Configurations With a Bite Sized Solution” by our senior consultants Kevin Vasconcellos and Jeff McNeal. This presentation will demonstrate how customized configurations can be captured in one or multiple constraints with small “policy classes”, enabling easy and dynamic run-time application or removal of configurations required by complex DUT simulation scenarios.

Since this year’s conference is virtual, many of our engineers will be in virtual attendance to connect with. This includes our CTO Jason Sprott, Vice President Vanessa Cooper and Senior Consultant Paul Marriott who will be hosting the “Advanced Verification 2″ session on March 2nd at 15:00 PST. As always, we look forward to meeting you and sharing ideas with the verification community.

For a look at our previously published conference papers and presentations, follow the link here.

See you (virtually) at DVCon 2021!

Exciting opportunites to join Verilab in the United States

August 14, 2020 by Paul Marriott
Are you a Verification Specialist in the field of #semiEDA with a deep knowledge of #SystemVerilog? Do you want to be an influencer, collaborator or coach? If so, we invite you to join our team! We have openings in both Redmond and San Jose in California as well as in Austin, Texas.

Specman editing support for Emacs

July 25, 2020 by Marcus Harnisch

Editing Specman/e files in Emacs has a long history, dating back at least 20 years, according to a reference to specman-mode found in an ancient mbox file on my computer. Over the years the code has moved to Cadence and then took a bit of a rest. The original domain (specman-mode.com) disappeared and later versions of specman-mode were occasionally circulated in Cadence’s community forums.
This encouraged my friend and colleague Scott Roland to continue maintenance on GitHub with the help of others including myself. Sadly he passed away and specman-mode found a new home again: https://github.com/ooglyhLL/specman-mode
In many years of using it I kept my own wishlist of things I’d like to see changed or at least make it easy to customize to personal taste. Achievements so far:

  • Extend/fix syntax highlighting. This is of course an ongoing effort.
  • Respect user’s preferences and assumptions when it comes to Emacs execution environment (local variables, hooks, syntax table) and preferred Specman line comment style (VHDL vs Verilog)
  • Increase use of up-to-date, built-in Emacs features. This paves the way for better integration with cross-cutting functionality.
  • Add GNU Global support via ggtags (https://github.com/leoliu/ggtags)
  • Dust off the code base. The single-file source weighed in at about 5000 lines total. Further reduction in size and complexity will make it easier to maintain and extend the code in the future.

On a separate branch I am currently experimenting with a major improvement in the context of “syntactic parsing” (using memoizing syntax-ppss for the afficionados) that allows us to get rid of a huge block of specific code that implemented effectively the same when Emacs didn’t have the feature, yet. This simplifies code in countless places (total savings amount to 1000 lines), makes it potentially more robust and already shows a run-time reduction by 80% when reindenting a file of significant size.
Due to stagnating development on XEmacs, support for it will likely come to an end sooner or later. Having been a long time XEmacs user myself I find it increasingly hard to justify the time and effort to ensure compatibility.

Your feedback and support will be much appreciated. Please use GitHub’s issue tracker for bug reports and requests.

Verilab at DVCon 2020

February 25, 2020 by Alex Melikian

The month of march is coming up and that means the DVCon US conference is around the corner. Once again, Verilab will be running a Short Workshop at this year’s conference, entitled “Parameterize Like a Pro”, to be held on Monday March 2nd at 3:30pm.

Our award winning  consultants, Jeff Montesano and Paul Marriott, will be doing the honors and hosting the session. They will present field-tested techniques,  as well as the tricks, skills and insight needed by verification engineers dealing with the challenges of verifying a highly configurable parameterized RTL designs and IP. Full details are available here:


On Wednesday March 4th, Paul Marriott, member of the DVCon technical program committee, will host the technical session entitled SystemVerilog Solutions taking place in the Fir Room from 3:00 until 4:30pm.

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Specman/e Syntax for Sublime Text 3

January 28, 2020 by Alex Melikian

This article was originally written by our Principal Consultant Thorsten Dworzak on this site. Minor edits were made here for formatting reasons.

According to the 2018 StackOverflow Developer Survey, the popularity of development environments (IDEs, Text Editors) among software developers shows the following ranking:

1. Visual Studio Code 34.9%

2. Visual Studio 34.3%

3. Notepad++ 34.2%

4. Sublime Text 28.9%

5. Vim 25.8%

6. IntelliJ 24.9%

7. Android Studio 19.3%

8. Eclipse 18.9%

15. Emacs 4.1%

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The Benefits of Anonymity - Feedback and Future Plans

December 13, 2019 by Adam Rose

What was your motivation for doing the whitepaper ?

Really there were two motivations. While the mere fact of a standardized verification language and methodology is a good thing, to misquote Churchill ( who was actually misquoting someone else ), I think it is fair to say that the UVM is the worst form of verification methodology except for all those other methodologies that have been tried from time to time. Really SystemVerilog and UVM are very clunky and frankly frustrating. It’s not that the Emperor has no clothes at all. It’s more that he has too many, and that his wardrobe is a bit faded, old fashioned and somewhat threadbare.

The other motivation was outlined in the introduction to the whitepaper. I have had a lot of fun with Ruby, Python and the latest versions of C++ recently and wanted to see how we could improve things by taking some of nice features from those language into SystemVerilog, and what effect that would have on the methodology. Once I started typing, I found I couldn’t stop, much to the bemusement of my family !

What was the reaction to the whitepaper ?

My initial worry about publishing the whitepaper was that no-one at all would be interested. However, I was really quite encouraged by the reaction. I have had a lot of positive comments and constructive criticism, as well as some healthy scepticism.

One very valuable insight that came from the feedback is that lambda syntax and closures are not exactly the same thing. Lambda syntax is just a mechanism for creating anonymous functions. Closures are a way of capturing data which is local to the anonymous function for use later when the function is called. On reflection, I think that the real gains come from the closure aspect of most anonymous function syntaxes.

peripheral suggestion that generated a surprising amount of discussion was a suggestion for some improvements to the package syntax. This proposal was motivated by minor naming monstrosities in the UVM such as uvm_tlm_analysis_port, but I’m sure most verification engineers can cite far worse examples. The solution to this problem is some mechanism to compose small packages into larger ones, and to be able to select a component of a large package if that’s all you are using.

Another interesting discussion developed in relation to the central claim of the whitepaper, which is that complicated macros indicate an inadequate language definition. A counter argument is that the relatively primitive C like macro language of SV should be enhanced so that it would be more capable. Having seen how macro-less languages like Ruby and Python work, I still hold to the view expressed in the whitepaper, but I would be interested to understand the counter arguments in more detail.

Are you planning a follow up ?

An internal Verilab reviewer commented on the following sentence : “it is clear that there are obvious applications to callbacks, ports, etc” by saying that it wasn’t at all clear and obvious ! On LinkedIn, another reviewer said that he was “somewhat in the I’m-not-sure-this-addresses-the-fundamental-problems boat”. I can well understand these points. I felt had I to cover quite a lot of ground explaining the basic ideas, so I couldn’t really go into sufficient detail in showing how they could be applied.

Readers may or may not be interested to know that I’m working on a sequel which does go
into more detail about how to apply these techniques, in the process extending and
clarifying the ideas presented in the first paper. The intention of the sequel is to show how
these ideas can be used to create a much smaller, sleeker, and more flexible SystemVerilog
based verification methodology.

DVCon Europe 2019 (Updated)

October 15, 2019 by Alex Melikian

[This posting was updated to include the additional "All Your Base Transactions Belong to Us" presentation by Jason Sprott]

Verilab is proud to be an event sponsor at the DVCon Europe 2019 in addition to be running a tutorial and presentation.  Verilab Senior Vice-President and multiple conference award winner Mark Litterick will be presenting the “Be a Sequence Pro” tutorial on Tuesday October 29th. Mark is also a member of the technical committee at this year’s conference. Topics in this tutorial include sequence implementation guidelines, tips for streaming data applications, improving verification productivity and support for a Portable Stimulus workflow. Full details are available here:


In addition, Verilab COO Jason Sprott will present “All Your Base Transactions Belong to Us”, based on our consultants Jeff Vance and Alex Melikian’s whitepaper, on Wednesday October 30th.

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SNUG Austin 2019

September 5, 2019 by Alex Melikian

Continuing a tradition, Verilab is proud to participate in our hometown conference at SNUG Austin 2019. Seasoned consultants Jeff Vance and Alex Melikian will present “All Your Base Transactions Belong to Us” on Wednesday, September 11th.

Based on their conference paper, the presentation will cover how the mixin design pattern can be utilized in SystemVerilog to supplement any transaction class in a UVM project with centrally defined metadata and functionality. The solutions presented can be applied to any verification project with minimal effort to achieve better management of code dealing with transaction processing. These can enhance control of system-wide dataflow, improve the quality of debug information and increase overall verification efficiency over the course of a project.

Complete details on the proceedings of this conference can be found here:


As always, Verilab looks forward to sharing ideas and engaging with the verification community. All our past published conference papers and presentations can be found here:


See you at SNUG Austin 2019!

Verilab at DVCon 2019

February 21, 2019 by Alex Melikian

Verilab is proud to be returning to DVCon in 2019 and will be running the “Be a Sequence Pro” workshop on Thursday February 28th. Last year’s best paper award winning co-authors Jeff Montesano and Jeff Vance will give a lecture style workshop covering guidelines of managing large-scale UVM sequence libraries. Topics covered will include sequence implementation guidelines, tips for streaming data applications, improving verification productivity and support for a Portable Stimulus workflow. Full details are available here:

Also in attendance at the conference will be our CTO Jason Sprott and vice president Vanessa Cooper. As always, we look forward to meeting you and sharing ideas in the verification community.

For a look at our past conference papers and presentations, follow the link here.

See you at DVCon 2019!

DVCon EU & SNUG Austin 2018

October 18, 2018 by Alex Melikian

This month, Verilab consultants will be participating in, and presenting at two conferences on two continents.

On October 23rd, award-winning authors Jeffrey Montesano and Jeff Vance will present “Use the Sequence, Luke! Guidelines to Reach the Full Potential of UVM Sequences” at SNUG Austin 2018. This presentation covers guidelines for optimizing control, effectiveness, debugging and reuse of UVM sequences, based on extensive project experience of complex designs. More details here.

Furthermore, multi-award winning consultant Mark Litterick will run a “UVM Audit: Assessing UVM Testbenches” tutorial at DVCon Europe on October 24th. This tutorial presents strategies and guidelines for auditing UVM code to identify and address reuse, flexibility and effectiveness of a testbench. More details here.

As always, we look forward to meeting people and sharing ideas in the verification community. For a look at our past conference papers and presentation, follow the link here:

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