- February 7, 2017
DVCon 2017: "SV Jinxed Half My Career" Panel Preview
- October 18, 2016
DVCon Europe 2016: Slicing Through the UVM’s Red Tape - A Frustrated User’s Survival Guide
- October 17, 2016
DVCon Europe 2016: Formal Verification - Too Good To Miss
svlib - a programmer's utility library for SystemVerilog January 4, 2015
svlib is a free, open-source library of utility functions for SystemVerilog. It includes file and string manipulation functions, full regular expression search/replace, easy reading and writing of configuration files, access to environment variables and wall-clock time, and much more. This project was presented at DVCon 2014.
Version 0.3 adds improved documentation, and one minor fix in the string library.
Version 0.4 improves documentation and source-file organization.
Version 0.5 further improves documentation, fixes some issues and adds Regex::split.
( Jonathan Bromley , Winkelmann, Andre )
- Version 0.5 source code and documentation
- DVCon 2014 paper - SystemVerilog, Batteries Included (.pdf)
- DVCon presentation with notes (.pdf)