This presentation addresses the requirements for verification of complex FPGAs using a mixture of simulation and design-for-verification approaches to establish correctness of the complex control-based functionality allowing for on-the-bench testing of full operational modes, data and traffic throughput. The targeting of key features for different stages in the process is discussed along with the need for repeatable regression results in both simulation and bench-based testing. Mentor Graphics Scotland and Ireland Designers Forum 2002.

( Mark Litterick )