svlib is a free, open-source library of utility functions for SystemVerilog. It includes file and string manipulation functions, full regular expression search/replace, easy reading and writing of configuration files, access to environment variables and wall-clock time, and much more.

Originally presented at DVCon 2014, the open source code is now available for download and participation on Bitbucket here:‍

https://bitbucket.org/verilab/svlib/src/master/svlib/‍

Users can create feature requests, bug reports or any other issues via the Bitbucket 'issues' link. Participants can also create pull-requests for the archive which would be reviewed by the project masters before merging into the master branch.

( Jonathan Bromley , Winkelmann, Andre )