SNUG 2009: Using the New Features in VMM 1.1 for Multi-Stream Scenarios    April 18, 2009

Today's verification solutions often require complex concurrent streams of stimulus controlled from higher level transactors or scenarios. The VMM 1.1 library has been enhanced to add this capability, and support the management of access to the resources shared by different stimulus streams, i.e. multiple streams providing stimulus to the same transactor. This paper describes the challenges faced in developing these new features, and takes a detailed look at how they are used in a VMM "multi-stream scenario" environment.

( Jason Sprott , JL Gray , Sumit Dhamanwala, Cliff Cummings )

• snug2009_vmm_multistream_scenarios-20090317.pdf (920 KB)

OCP-IP Article - OCP Profiles and Transactions    January 5, 2009

Published in the DEC 2008, Vol 7 edition of the OCP-IP Newsletter (http://www.ocpip.org/)
This article demonstrates how two key aspects of OCP "profiles and transactions" were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems. The article uses the Verilab OCP uVC as an example. This uVC is a mixed-language OCP compliant verification component that supports a major subset of Open Core Protocol Specification 2.2. ( Mark Litterick )

• Article (2.42 MB)
• White Paper (full version) (1.50 MB)

ClubT 2008 - Intro to Requirements Based Verification    October 7, 2008

A short overview of Requirements Based Verification as presented at ClubT 2008 in Bristol. ( David Robinson )

• PDF (2.04 MB)

Improve Your SystemVerilog OOP Skills by Learning Principles and Patterns    October 7, 2008

SVUG2008 Fall presentation. This presentation looks at how you can improve your object-oriented programming skills by exploiting the wisdom of others. We introduce some key object-oriented design principles and look at what design patterns bring to the party. ( Jason Sprott )

• Presentation (845 KB)

Multi-Stream Scenarios - Enhancing Stimulus Generation in the VMM    October 7, 2008

Boston SNUG2008 (Presentation Only). Takes a look at the new Multi-Stream Scenario features Verilab developed for Synopsys, to upgrade the VMM's capabilities. These features are scheduled to be released in VMM 1.1.

( Jason Sprott , Sumit Dhamanwala )

• Presentation (752 KB)

Endian: From the Ground Up    August 18, 2008

This document explores endianness using a coordinate system terminology, and explains common endian misconceptions as arising from coordinate system ambiguity. Topics covered are: The definition and properties of endian; the endian problem; independence of bit and byte endian; why bit significance and byte address must be managed in hardware; why byte significance must be managed in software. ( Kevin Johnston )

• Endian: From the Ground Up (338 KB)

Functional Coverage in SystemVerilog    October 9, 2007

SVUG 2007 Presentation on Functional Coverage in SystemVerilog, comparing covergroups and cover properties, and some tips on coding for analysis. ( Jason Sprott )

• Pressentation (491 KB)

SVUG Europe 2007: Assertion-Based Verification using SystemVerilog    October 8, 2007

Overview of ABV using SystemVerilog Assertions, including: general syntax and components, formal arguments, local variables, multiple clocks
Detailed analysis of complex worked examples, including: combinations of SVA constructs, demonstrate capability of SVA ( Mark Litterick )

• Presentation (455 KB)

Application Note: FPGA Protoyping in Verification Flows    December 8, 2006

Hardware-assisted verification environments often make use of FPGAs to prototype the
ASIC in order to provide a faster alternative to simulation and allow software development to proceed in parallel with hardware design. This application note addresses the factors that should be taken into account in such a flow in order to maximize the effectiveness of the overall verification environment. ( Mark Litterick )

• Application Note (158 KB)

The Myth of SystemVerilog Interoperability    July 30, 2008

In this 45 minute presentation first given at DAC 2008, JL Gray, member of the Accellera VIP TSC and author of Cool Verification (www.coolverification.com) looks at the verification interoperability problem by examining SystemVerilog interoperability between simulators and functional differences between competing methodology libraries.  JL will also discuss the likelihood SystemVerilog interoperability will move (unlike Santa and the Tooth Fairy) from myth to reality as a result of the efforts of the Accellera VIP TSC. ( JL Gray )

• The Myth of SystemVerilog Interoperability (1.65 MB)

Getting Started with Requirements Based Verification    June 17, 2008

Verification planning is an essential part of the chip design process, yet experience shows that it is seldom attempted with any rigor.  Enthusiasm for the task tails off rapidly as soon as the "real work" of coding the testbench becomes feasible.  Limited knowledge of how to do effective verification planning, low personal motivation and benefits, and lack of permission are common reasons for abandoning the planning early. Subsequent verification tends to be inefficient, impacting both the quality of the design and delivery schedule, and leading to a stressful and unsatisfying project experience for all involved.

In this one hour presentation first given at DAC 2008 in Anaheim, California, Dr. David Robinson from Verilab provides an introduction to Requirements Based Verification, a verification planning approach which aims for efficiency by allowing project stakeholders visibility into the size, scope, progress and risk of the overall verification process. Good risk-based visibility at all stages helps ensure that verification proceeds with few surprises.

This presentation is extracted from Verilab's Requirements Based Verification review process, and covers the following topics:

• Requirements Based Verification overview
• How to create good requirements
• Risk based prioritization

The presentation will be of interest to verification engineers and managers who would like to improve the efficiency of their verification efforts.

( David Robinson )

• Requirements Based Verification (1.57 MB)

An Introduction to Aspect Oriented Programming in e    June 21, 2006

White Paper 2006 ( David Robinson )

• Paper (694 KB)

Simplify SoC Verification using a Generic Approach    June 1, 2006

CDNLive! June 2006, Nice, France ( David Robinson )

• Presentation (251 KB)

Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions    February 1, 2006

DVCon 2006 (Best Paper Winner) ( Mark Litterick )

• Presentation (613 KB)
• Paper (369 KB)

Using SystemVerilog Assertions in Gate-Level Verification Environments    February 1, 2006

DVCon 2006 ( Mark Litterick )

• Paper (186 KB)
• Presentation (525 KB)

Simplify SoC Verification using a Generic Approach - NMI    February 1, 2006

NMI Verification Network Event Feb. 2006 ( David Robinson )

• Presentation (611 KB)

Shorten and Simplify SoC Verification using a Generic eVC    November 1, 2005

White Paper ( David Robinson )

• Paper (191 KB)

Focusing Assertion Based Verification Effort for Best Results    November 1, 2005

Mentor Graphics Solutions Expo Scotland 2005 ( Mark Litterick )

• Presentation (393 KB)

Using SystemVerilog Assertions for Functional Coverage    July 1, 2005

DAC 2005 (white paper presented on Accellera booth) ( Mark Litterick )

• Paper (175 KB)
• Presentation (589 KB)

Utilizing Vera Functional Coverage in the Verification of a Protocol Engine for the FlexRay(TM) Automotive Communication Sytem    May 1, 2005

SNUG Europe 2005 ( Mark Litterick , Marcus Brenner - Freescale Semiconductor )

• Paper (148 KB)
• Presentation (170 KB)

Verifying In-situ Embedded Software Using Coverage Driven Verification    October 1, 2005

Verisity ClubV 2005 ( David Robinson )

• Presentation (1.52 MB)

An Assembler Driven Verification Methodology (ADVM)    April 1, 2005

Date 2005 ( John MacBeth , Ken Gray , Dietmar Heinz - Infineon Technologies AG )

• Paper (175 KB)
• Presentation (589 KB)

Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments    January 1, 2005

MTV 2004 ( Mark Litterick , Joachim Geishauser - Motorola GmbH )

• Paper (181 KB)
• Presentation (555 KB)

"Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments (SNUG Europe 2004)    January 1, 2005

SNUG Europe 2004 ( Mark Litterick )

• Paper (245 KB)
• Presentation (1.25 MB)

Learn to do Verification [in Vera] with AOP? We've just learned OOP!    January 1, 2005

SNUG Europe 2004 ( David Robinson )

• Paper (59 KB)
• Presentation (523 KB)
• Supporting Code (6 KB)

A Scalable Method of Propagating Event Messages Throughout a Vera Testbench    January 1, 2005

SNUG Europe 2003 ( David Robinson )

• Paper (58 KB)
• Supporting Code (11 KB)

FPGA-Centric Functional Verification    May 22, 2002

Mentor Graphics Scotland and Ireland Designers Forum 2002 ( Mark Litterick )

• Presentation (155 KB)