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Table Of Contents    October 28, 2018


UVM:
SystemVerilog:
Specman/e:
Verification:
OVM/VMM/AVM/Vera:


To Infinity And Beyond - Streaming Data Sequences In UVM    March 2, 2021

This paper introduces the concept of autonomous stimulus generation using streaming data techniques and discusses its application in the verification of complex sensor style devices. With a focus on digital simulation of SoCs containing real-number models for the analog sub-components, we demonstrate how to implement autonomous analog and digital data streaming patterns using UVM sequences and drivers. ( Mark Litterick , Jeff Montesano , Jeff Vance )



Configuration Conundrum: Managing Test Configuration with a Bite Sized Solution    March 2, 2021

The authors will show the reader how to take advantage of a design pattern called the Policy Pattern to make configuration of a UVM testbench easier for the user to modify. Using this pattern will allow test writers to quickly and easily modify the configuration of the DUT or testbench while also providing at-a- glance information about what configuration a test is using. This technique eliminates the need to know some testbench details: how the components of the testbench work; how components are built; and how to write complex constraint blocks This isolation also allows the testbench writers to modify how the internals of the testbench components are coded without disrupting tests or the test writers.

( Jeff McNeal , Kevin Vasconcellos )



Specman Primer For SystemVerilog Users    May 12, 2020

A guide for knowledgeable SystemVerilog users who need to use Specman and the e language on their job but already have an understanding of constrained-random verification. Looking beyond just the syntax, you will find that there are more similarities than differences between the two languages. Some concepts are unique to the e language, and will be given specific attention. This guide is the culmination of many informal project training and consulting over the past few years. ( Thorsten Dworzak )


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Parameterize Like a Pro    March 2, 2020

This short tutorial was delivered at DVCon-US 2020 by our consultants Paul Marriott and Jeff Montesano. It covers a range of issues and concerns that must be addressed when you need to create UVM verification environments that can handle parameterized designs such as bus fabric, memory controllers and fast serial interfaces.


In addition to the tutorial slides and notes, you will find here an annotated collection of papers, written by Verilab consultants and others, that provide useful techniques and insights.
( Jeff Montesano , Paul Marriott )



White Paper: The Benefits of Anonymity - A Modest Proposal to Enhance the SystemVerilog Verification Language    November 15, 2019

Have you ever thought "why do I have to use all these uvm_field_* macros when I’ve already declared my transaction variables ?”. Or "what on earth is trans::type_id::create” ? Or "why are there so many types of uvm_do macros ?”. This white paper makes a number of related suggestions to improve SystemVerilog and bring it up to date with recent developments in languages such python and C++. ( Adam Rose )



DVCon Europe 2019: Be a Sequence Pro to Avoid Bad Con Sequences    October 29, 2019

This tutorial provides a comprehensive overview of sequences and how we use them to orchestrate effective constrained-random stimulus in UVM testbench environments. The operation of these sequences on virtual and physical sequencers is presented in the context of proactive masters, reactive slaves and autonomous data stream generators. Guidelines for encapsulating sequences, architecting sequence libraries, managing complexity and enabling reuse are also provided. Techniques to maximize project productivty and improve progress tracking by leveraging the sequence API are discussed as well as the relationship between the sequence architecture and portable stimulus extensions using PSS.

  • Introduction to sequences – what are they & why do we care
  • Sequence execution – masters, reactive slaves, streaming data
  • Sequence guidelines – improve control, complexity, & reuse
  • Verification productivity – strategies to manage features
  • Portable Stimulus Considerations – how PSS impacts sequences
( Mark Litterick , Jeff Vance, Jeff Montesano )



SNUG Austin 2019: All Your Base Transactions Belong to Us    September 10, 2019

  • Technical Committee Award for Best Paper
This paper demonstrates how the mixin design pattern can be utilized in SystemVerilog to supplement any transaction class in a UVM project with centrally defined metadata and functionality. The solutions presented can be applied to any verification project with minimal effort to achieve better management of code dealing with transaction processing. 

Also presented as an invited paper at DVCon Europe 2019.

( Jeff Vance , Alex Melikian )


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DVCon US 2019 WorkShop: Be a Sequence Pro    March 12, 2019

This lecture style workshop covers guidelines for managing large-scale UVM sequence libraries. Topics covered include sequence implementation guidelines, tips for streaming data applications, improving verification productivity and support for a Portable Stimulus workflow.


( Jeff Vance , Jeff Montesano , Mark Litterick )



DVCon Europe 2018: UVM Audit Tutorial    October 24, 2018

Assessing UVM Testbenches to Expose Coding Errors and Improve Quality 

Does your UVM codebase contain hidden traps that may undermine current or future projects? Working on many client projects we have seen verification environments that superficially appear to follow UVM best practice, but don’t stand up to expert scrutiny. In this tutorial we present our guidance for audit of existing and new UVM code, giving you a technically robust approach to planning and review of your UVM project. UVM Audit addresses the truly important issues of reuse, flexibility and verification effectiveness. It identifies a range of frequently-encountered problems, and provides easily-understood guidance that you can apply to legacy, current, and future projects. 

( Mark Litterick , Jonathan Bromley, Jason Sprott, Tamás Simon )



SNUG Austin 2018: Use the Sequence, Luke - Guidelines to Reach the Full Potential of UVM Sequences    October 23, 2018

  • Technical Committee Award for Best Paper
Universal Verification Methodology (UVM) sequences are the standard way of controlling scenarios for design verification. Presently, no methodology exists to define an optimal collection of sequences for a UVC (UVM verification component) and/or a UVM testbench. A sub-optimal sequence library typically leads to overly complex testbenches that are hard to control, debug, and maintain. These problems pose risks to both project schedule and tapeout quality. This paper presents guidelines that solve these problems. We show how to isolate constraint solver steps through sequence application programming interface (API) layers that lead to rapid debug, improved sequence reuse, and easier control for test writers. Encapsulation guidelines demonstrate how to enhance sequences using configuration objects and package utility methods. Many of these guidelines come from extensive project experience dealing with complicated problems that occur on a large scale. ( Jeff Vance , Jeff Montesano , Mark Litterick )



DVCon2018: My Testbench Used to Break! Now it Bends    February 27, 2018

  • Best Paper Award Winner
This paper demonstrates a technique that allows a single UVM testbench to adapt to design configuration changes that would otherwise require significant manual effort. The solution accommodates multiple design versions, changes in design hierarchy, and testbench migrations to future project iterations. It also allows us to simulate any subsystem in isolation without maintaining a separate testbench. To achieve this, we show several enhancements to the UVM harness technique along with a run-time generated environment topology that mirrors the design hierarchy. Examples show how this results in a testbench that automatically adapts and works with any design configuration. ( Jeff Vance , Jeff Montesano , Kevin Johnston , Kevin Vasconsellos )


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SNUG Austin 2017: Verification Prowess with the UVM Harness    October 26, 2017

  • Technical Committee Best Paper Award
In this paper we show how to create a UVM testbench with interface connections that universally work in any design simulation context. A harness is a common solution for encapsulating interfaces, binding them to the DUT, and publishing virtual interface assignments. We show how to enhance the harness with interfaces that work with both master and slave agents, in active and passive modes, with active RTL or stub modules, and can tolerate changes to design hierarchy. We accomplish this using interfaces with standard SystemVerilog features of binding and port coercion. Examples demonstrate how we can now encapsulate methods that access internal signals, change UVM agent roles between tests, and dynamically inject stimulus to any portion of a design without impact to how we connect and use interfaces from testbench components. This also allows us to efficiently run tests that verify different portions of a design using a single compile. 
( Kevin Johnston , Jeff Montesano , Jeff Vance )



DVCon Europe 2017: The Universal-Verification-Methodology Multi-Language Library    October 26, 2017

The Universal-Verification-Methodology Multi-language (UVM-ML) library is a simulator independent extension of the UVM and promises easy integration of different high-level verification languages. We applied it together with previously existing techniques to attach a SystemC model to different UVM SystemVerilog testbenches. The interface between the two worlds has been implemented using TLM2, DPI-C, and FMI. Over the course of this project we faced some obstacles and stumbling blocks concerning different aspects. By sharing our experience and some tips and hints, we hope to provide others with a smoother experience. ( Thorsten Dworzak , Angel Hidalga )



SNUG Canada 2017: Perplexing Parameter Permutation Problems? Immunize Your Testbench    May 14, 2017

RTL parameters are used frequently in designs, especially IPs, in order to increase flexibility for reuse or different target applications and products. As demand for feature density or power efficiency increases, the number of permutations of valid RTL parameters becomes increasingly difficult to manage. A well structured and flexible verification testbench is therefore required to handle the multiplicity of combinations of these parameters. Failure to account for this could result in a testbench that would become difficult to maintain, or, worse, no longer adequate to find potential bugs in all possible permutations of the parameters. This paper proposes solutions for structuring various segments of a UVM test bench to handle designs with large amounts of DUT parameter combinations, minimizing maintenance effort and risk of bug escapes.     ( Alex Melikian , Paul Marriott )



DVCon Europe 2016: Slicing Through the UVM's Red Tape - a frustrated user's survival guide    October 20, 2016

The Universal Verification Methodology (UVM) has brought extensive benefits to the field of functional verification using SystemVerilog. However, applying it to real projects can bring challenges and frustrations for novice and intermediate-level users. This paper examines typical examples of such challenges, and offers solutions that respect fundamental aims of the UVM: consistency, reusability, and expressive power. Examples include integration of directed tests or external models into the sequences mechanism, reconciling the abstract and untimed nature of sequences with the need for precise control over stimulus timing, proper use of the configuration or resource databases and when it is better not to use them, and working with a parameterized device under test.

( Jonathan Bromley )


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DVCON Europe 2016: Formal Verification - Too Good To Miss (Tutorial)    October 19, 2016

We find that getting started on formal verification can be a challenge. It’s different to traditional simulation, with some unfamiliar concepts. However, for the right kind of problem, it’s just too good to miss out on due to the lack of experience.  This tutorial aims to address that initial lack of confidence and basic knowledge, helping engineers to get started on real project work using formal verification. We’ll be using a small case study to take attendees through the lifecycle of a formal verification project for a block-level RTL design. 

( Jonathan Bromley , Jason Sprott )



SNUG Austin 2016: Configuring a Date with a Model - A Guide to Configuration Objects and Register Models    September 29, 2016

The topic of register models, configuration objects, and their interaction can be an area of great complexity and sometimes confusion for many verification engineers.  Fundamentally, a register model holds the contents of each register in the design for use by the verification environment, while a configuration object holds the configuration for the interface protocol agents, verification components and verification environment.  So while one is implementation specific (register model) and one is generic (configuration object), they both hold configuration information and are both required in a given testbench.  In this paper we will describe the unique roles of register models and configuration objects, explain why they should both be used in a verification environment, and present a framework in SystemVerilog/UVM for making the testbench and design configurations remain in sync for different types of designs. ( Jeff Vance , Jeff Montesano )



SNUG UK 2016: Effective SystemVerilog Functional Coverage: design and coding recommendations    June 30, 2016

  • Technical Committee Honourable Mention Award

The design and coding of SystemVerilog covergroups can be laborious and error-prone, partly because of the inherent difficulty of the task, but also because the language's features have traditionally provided limited support for configurable and reusable coverage. Fortunately, support is now available in VCS and other simulators for many of the interesting coverage features introduced in the 2012 revision of SystemVerilog. We give examples, guidelines and recommendations showing how these features can make your code more concise, expressive and versatile. The Universal Verification Methodology brings its own special considerations, so the paper also offers specific coding patterns for configurable and reusable coverage within UVM testbench classes. 

(Also included in SNUG Austin 2016 proceedings.)

( Jonathan Bromley , Mark Litterick, Vanessa Cooper )



SNUG Germany 2016: Mastering Reactive Slaves in UVM    June 23, 2016

In most interface protocols a component can either be a master, which initiates the transactions or a slave, which responds to these transactions. Generating constrained-random request transactions in a proactive master agent using sequences is fairly straightforward in the UVM; however, implementing a reactive slave is much more complicated. This paper outlines the roles and responsibilities of a reactive slave and proactive master and then explores different architectures for reactive slave implementation. All aspects of reactive slave operation are illustrated with code examples, including architecture, sequence items, forever sequences, TLM interconnection, storage API, synchronization and error injection as well as UVC topology. This is an enhanced version of the paper that was published in SNUG Austin 2015.

( Jeff Montesano , Mark Litterick )


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DVCon 2016: Full Flow Clock Domain Crossing - From Source to Si    March 1, 2016

Functional verification of clock domain crossing (CDC) signals is normally concluded on a register-transfer level (RTL) representation of the design. However, physical design implementation during the back-end pre-silicon stages of the flow, which turns the RTL into an optimized gate-level representation, can interfere with synchronizer operation or compromise the effectiveness of the synchronizers by eroding the mean time between failures (MTBF). This paper aims to enhance cross-discipline awareness by providing a comprehensive explanation of the problems that can arise in the physical implementation stages including a detailed analysis of timing intent for common synchronizer circuits. ( Mark Litterick )



DVCon Europe 2015: Advanced UVM Tutorial - Taking Reuse To The Next Level    November 11, 2015

This tutorial provides intermediate and advanced users of the Universal Verification Methodology (UVM) with comprehensive in-depth material on all aspects of achieving vertical and horizontal verification reuse using UVM. The content is derived from Verilab’s extensive experience in solving reuse issues for many different clients, projects and applications using a variety of verification languages and includes pragmatic guidelines as well as real-world examples. It is aimed at engineers with a good understanding of SystemVerilog and practical experience in either OVM or UVM. UVM beginners may also find the content interesting although the details could be somewhat overwhelming, at any rate it should raise awareness and provide some good reference material for the future. The material is grouped into the following topics:

  • Vertical & Horizontal Reuse of UVM Environments
  • Self-Tuning Functional Coverage - Strategy & Implementation
  • Adaptive Protocol Checks - Configuration Aware Assertions
  • Configuration Object Encapsulation & Appropriate config_db Usage
  • Parameterized Classes, Interfaces & Registers

 

( Jason Sprott , Mark Litterick , Jonathan Bromley )



SNUG Canada 2015: Replacing Hardcoded Register Values with Hardcore Abstraction    October 1, 2015

Today’s complex protocols typically involve built-in register functionality for configuration and operation purposes. This requires corresponding VIPs to mimic register functionality in order to enable exact behaviour and complex operations. VIP developers may resort to using a large number of hardcoded values representing register addresses, reset values or field locations.

However, this approach is prone to errors and demands a high level of maintenance during the course of a project as register definitions often change. Our solution enables VIP developers to include register functionality in a manner that is not only scalable, but also flexible and robust to any changes. The solution involves leveraging the derived UVM register model classes, typically defined for mirroring and automating checks on DUT registers. These derived register classescan be used to create a layer of abstraction, allowing the VIP to be transparent to all pre-defined register related values in the protocol. ( Hilmar Van Der Kooij , Alex Melikian )



DVCon Europe 2015: Is Your Testing N-wise or Unwise?    September 17, 2015

  • DVCon Europe 2015 - Best Paper Award
Also presented at SNUG Austin 2015 and MTV Austin 2015.

Pairwise, and more generally N-wise, pattern generation has long been known as an efficient and effective way to construct test stimulus and configurations for software testing. It is also highly applicable to digital design verification, where it can dramatically reduce the number and length of tests that need to be run in order to exercise a design under test adequately. Unfortunately, readily available tools for N-wise pattern generation do not fit conveniently into a standard hardware verification flow. This paper reviews the background to N-wise testing, and presents a new open-source SystemVerilog package that leverages the language's constrained randomization features to offer flexible and convenient N-wise generation in a pure SystemVerilog environment.

The paper and presentation here are the versions that appeared at DVCon-Europe in November 2015. A freely downloadable SystemVerilog code package is included.
( Kevin Johnston , Jonathan Bromley )


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SNUG Austin 2015: Mastering Reactive Slaves in UVM    September 17, 2015

  • Technical Committee Best Paper Award

In most interface protocols a component can either be a master, which initiates the transactions, or a slave, which responds to these transactions. Generating constrained-random request transactions in a proactive master agent using sequences is fairly straightforward in the UVM; however, implementing a reactive slave is much more complicated, especially for relatively inexperienced users. The implementation can be further complicated if the slave has a storage component or we are required to synchronize high-level scenarios with slave traffic.

This paper outlines the roles and responsibilities of a reactive slave and proactive master and then explores different architectures for reactive slave implementation, highlighting their suitability for a protocol depending on the decoding of the transactions in the monitor.

( Jeff Montesano , Mark Litterick , Reddy, Taruna (Independent) )



SNUG Silicon Valley 2015: RESSL UVM Sequences to the Mat    March 23, 2015

Read-Evaluate-Start-Sequence-Loop (RESSL - pronounced "wrestle") is inspired by the Read-Evaluate-Print-Loop (REPL) found in Lisp and Python. The REPL in these languages encourage a rapid, iterative and interactive development process allowing the user to easily develop and test new sequences with a minimum of overhead. In the context of ASIC verification, RESSL enables the iterative development and debug of UVM sequences. Similar to the Lisp REPL, it includes four phases:

  • Read: A simple interpreter allowing the user to input commands via STDIN.
  • Evaluate: The evaluator takes those commands and executes them. These commands include among others, the ability to clone, alter parameters and start sequences.
  • Start-Sequence: The system starts the sequence (and any sub-sequences) defined.
  • Loop: Clean up and return back to the Read phase.
This paper provides details on the usage model, implementation and future work planned for the RESSL. A specially modified version of UVM-1.2 (with introspection) is required to use ressl and is supplied. You will need to also download svlib v0.4

 ( Bryan Morris , Jeff McNeal )



DVCon2015: Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation    March 4, 2015

This paper discusses a team's experience with taking complete block-level formal testbenches and making productive use of them in a dynamic (simulation) environment. We describe the motivations for this re-use and the challenges encountered. The paper presents detailed methodology suggestions that we used successfully to overcome these challenges, and reports how both formal and dynamic verification quality was improved by re-using formal assets in this way throughout a project. ( Jonathan Bromley )



DVCon 2015: Lies, Damned Lies, and Coverage    March 4, 2015

  • Honorable Mention Award
Functional coverage is a key metric for establishing the overall completeness of a verification process; however, empirical evidence suggests that coverage models are often inaccurate, misleading and incomplete. This paper proposes that such coverage defects are extremely common and since coverage analysis tends to focus on holes, or missing coverage, rather than the accuracy of what is already reported, then this represents a significant risk to the overall quality of the verification process. After a generic introduction to the problem the paper discusses practical examples and proposes pragmatic solutions for minimizing the risk and improving quality. Finally we demonstrate a novel application of the UCIS API to cross-reference different aspects of functional coverage in order to validate correctness of the model under some circumstances. 

( Mark Litterick )


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DVCon 2015: Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling    March 4, 2015

Coverage modeling is an essential component of today’s verification methodologies, but it’s often badly planned and poorly executed. The topics discussed in this paper are based on the experiences of the authors, working on SoC and IP projects for more than a decade. The aim of this paper is to enable readers to do a better job of developing their coverage models, by understanding the objectives and requirements more clearly, using some best practice styling, and taking reviews of implementation more seriously. ( Jason Sprott , Paul Marriott , Matt Graham, Cadence Design Systems Inc. )



DVCon Europe 2014: Advanced UVM Tutorial    October 14, 2014

This tutorial provides intermediate and advanced users of the Universal Verification Methodology (UVM) with some more in-depth material on key topics that will help take their understanding and effectiveness to the next level. It is aimed at engineers with a good understanding of SystemVerilog and practical experience in either OVM or UVM. After a very brief introduction to UVM in order set the scene and put the other topics into context, the tutorial takes a more detailed look at four topics that have been selected based on Verilab's combined experience implementing pragmatic UVM solutions on many projects at different clients:
• Demystifying the UVM Configuration Database
• Behind the Scenes of the UVM Factory
• Effective Stimulus & Sequence Hierarchies
• Advanced UVM Register Modeling & Performance ( Jason Sprott , Mark Litterick , Jonathan Bromley , Vanessa Cooper )



SNUG Austin 2014: Handling Windows of Uncertainty - Reducing False Errors from Variable DUT Timing    September 23, 2014

A common verification challenge is performing transaction level checks during windows of time when signal values are hard to predict. A testbench may generate predicted values too early or too late relative to the design under test, although the design behavior is nevertheless valid. This generates many false errors, increasing the effort to debug regressions and enhance testbench code. While many solutions exist for solving this problem, most have various deficiencies, typically adding leniency in the checking and increasing code complexity.

This paper proposes a generic window handler as a solution to overcome these issues in many practical situations. The window handler encapsulates timing characteristics of the hard-to-model behavior, reducing complexity of the testbench code without sacrificing rigor in transaction checks. When applied to an example design, this technique eliminated many false errors from simulations, allowing more time to find real bugs and quickly achieving error-free regressions.

( Jeff Vance )



CDN Live EMEA 2014: Macros to the Rescue    May 21, 2014

With the so-called "define-as-computed" macros, the e-language already has powerful extension capabilities that allow the engineer to create expressive short-cuts in order to hide the details of such low-level tasks as the key management example. These make code more concise and easier to understand. This paper presents a collection of macros which will simplify the everyday programming tasks that many verification engineers inevitably face sooner or later. Macros allow the definition of new actions, expressions, struct members, coverage items and a lot more. Other examples shown will include a repetition operator for scalar vectors (similar to that feature of Verilog), advanced regular expression matching against a list of regular expressions and a new cover item macro for time values as well as scalars larger than 32 bits. ( Thorsten Dworzak , Andre Winkelmann )


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SNUG 2014: "Reverse Gear" - Re-imagining Randomization with the VCS Constraint Solver    May 20, 2014

Technical Committee Best Paper award at SNUG Silicon Valley 2014

Creative use of the constraint solver built in to your SystemVerilog simulator can not only provide valuable random stimulus, but also can offer a highly productive way to solve certain programming problems. This paper looks at SystemVerilog randomization from a novel perspective, considering it not so much as a way to generate random numbers, but as a flexible and intuitive way to find a set of values that satisfy user-specified rules (constraints). ( Paul Marriott , Jonathan Bromley )



DVCon 2014: Advanced UVM Register Modeling - There's More Than One Way to Skin A Reg    March 5, 2014

This paper provides an overview of register model operation in the UVM and then explains the key aspects of base class code that enable effective complex register modeling. Several possible solutions to common modeling problems are discussed in detail with a focus on supporting both active and passive operation.  In addition the performance impact of large register models is analyzed and improved solutions provided. ( Mark Litterick , Marcus Harnisch )



DVCon 2014: Demystifying the UVM Configuration Database    March 4, 2014

The configuration database in the UVM is a highly versatile feature that allows the passing of objects and data to various components in the testbench. However, despite its versatility, the configuration database (uvm_config_db) can be a source of great confusion to those verification and design engineers who are trying to learn UVM. The goal of this paper is to demystify the uvm_config_db for the novice user. This paper will examine the functionality of the uvm_config_db starting with its relationship to the resource database. It will discuss how the database is implemented in the UVM library, and it will explore how to add to and retrieve from the database. In addition, practical examples will illustrate how to use the database in various scenarios. ( Paul Marriott , Vanessa Cooper )



DVCon 2014: A Guide To Using Continuous Integration Within The Verification Environment    March 5, 2014

In 2012, we introduced EDA to the power of Continuous Integration (CI) with “A 30 Minute Project Makeover Using Continuous Integration”. Now, two years later, there is still some confusion between the roles of Continuous Integration and EDA regression tools, when it comes to verification management and test execution. Also, some of the challenges faced when integrating CI with EDA tools, touched on in the previous paper, need to be expanded upon using concrete examples. While the technology for CI has been available for years, the methodology and mechanics of how best to use these tools in an EDA environment is not always obvious. In this paper we will clarify the roles of CI and regression management, and provide a practical guide on how users can quickly deploy CI within their verification environment. ( Jason Sprott , André Winkelmann, Gordon McGregor, Paul Marriott )


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DVCon 2014: Verification Mind Games - how to think like a verifier    March 4, 2014

Effective verification requires engineers to approach problems using a very different way of thinking compared to that normally applied by designers.  Specifically, the verification mindset is focused on finding the bugs that are virtually guaranteed to be in the design by stressing protocols, exploring corner cases, and applying a policy of zero tolerance towards design inconsistencies.  Designers on the other hand are concerned with constructing components that correctly implement the intended protocol with appropriate performance and without defects.  This paper provides examples of common verification problems that are susceptible to more than one approach, and explores solutions that are consistent with a proper verification mindset, while highlighting the risks associated with a more design-centric approach. ( Jeff Montesano , Mark Litterick )



DVCon 2014: SystemVerilog, Batteries Included: A Programmer's Utility Library for SystemVerilog    March 4, 2014

As the language of choice for many verification engineers, SystemVerilog is expected to act not only as a specialist verification language, but also as a hardware description language and a general purpose programming language. Although SystemVerilog's object oriented programming features and rich set of native data types provide excellent support for general purpose programming, many users including the authors have been frustrated by its lack of utility features that would be taken for granted in other languages. In this paper we present the results of our efforts to develop a comprehensive, consistent, easy-to-use utility library for SystemVerilog. We believe this to be the first announcement of such a library that is vendor-independent and carefully tailored to the needs of SystemVerilog users.

Code download and more information - http://www.verilab.com/resources/svlib/ ( Jonathan Bromley , André Winkelmann )



SNUG Austin 2013: Applications of Custom UVM Report Servers    September 1, 2013

  • Technical Committee Best Paper Award
The Universal Verification Methodology (UVM) provides a feature-rich set of reporting 
and message handling objects. These message handlers are being improved in UVM 
version 1.2 to provide an OOP-style messaging infrastructure. This paper discusses the 
existing handlers in UVM 1.1 and previews the implementation coming in UVM 1.2. 
A common task in many verification environments is customizing the log format and this 
paper will show how to do this for the UVM 1.1 and UVM 1.2 base class libraries. 
Methods to extend both implementations to produce log files using markup text formats 
will be discussed. Several use cases for these structured text files are also considered, 
with examples using an XML based approach that can be extended to other markup 
formats or SQL database storage, as needed. An interactive GUI, built to manipulate this 
structured log format, is demonstrated that enables complex filtering and dynamic 
message reconstruction as well as command line filtering approaches to produce custom 
reports. 
( Gordon McGregor )



CDN Live EMEA 2013: Using the Extension Capability and the Reflection Interface of Specman/e for Automatic Memoization    May 9, 2013

The e hardware verification language provides a powerful macro-definition syntax which can be used to extend the language, i.e. create new constructs that have syntax checking, and the look-and-feel of built-in constructs. Furthermore, it has a reflection API to query and control the properties of simple and compound types and objects.

In this paper we will show how these mechanisms are used to create an automatic memoization macro for pure methods (in e, what is generally called a function is called a method, while function arguments are called parameters).

Memoization is an optimization technique that trades run-time for memory space. Run- time critical methods can be sped-up using caching: the input and output parameter values of a method call are saved in a lookup-table. Upon each call of the method, the input values are compared with the cached ones. In case of a match, the function will return the cached result instead of recalculating it. If the cost of the cache-lookup and update is lower than calculating the result, it might be beneficial to memoize the method.
( Thorsten Dworzak )


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SNUG Silicon Valley 2013: Sub-cycle Functional Timing Verification Using SystemVerilog Assertions    March 26, 2013

This paper describes a novel, more complete approach to functional verification of sub-cycle timing using SystemVerilog assertions in an OVM verification environment. This approach found many bugs otherwise missed in OVM-only simulations. This functional sub-cycle timing behaviour includes maintaining fixed delays and phase relation- ships between inputs and outputs and ensuring there are no glitches on clocks or delayed signals. SystemVerilog assertions are evaluated on successive occurrences of an event or timing expres- sion. This presents a challenge for sub-cycle timing verification, where there is no obvious ref- erence clock suitable for triggering the assertions. Assertions sample their expressions in the preponed region of the simulation time slot, but the requirements called for sampling both before and after each triggering point. Examples of assertions showing how to overcome this and many other issues will be shown along with recommendations on how to write assertions for functional timing verification. ( Anders Nordstrom )



Verification Horizons Feb 2013: OVM to UVM Migration, or 'There and Back Again, a Consultant's Tale'    February 27, 2013

http://www.mentor.com/products/fv/verificationhorizons/horizons-feb-13

Many companies have a goal to migrate to UVM but this must be achieved without disrupting on-­‐going projects and environments. In our current clients we have all possible combinations of migration paths, a desire to move new projects to UVM and a definite need to support OVM for a good few years. This article presents an interesting OVM to UVM migration story where we successfully translated a whole family of verification components from OVM 2.1.2 to UVM, assessed the impact, and then reworked the original OVM code, which was still live in a series of ongoing derivative projects, to make the ongoing translations totally automatic and part of the project release mechanism.

( Mark Litterick )



DVCon 2013: SVA Encapsulation in UVM - enabling phase and configuration aware assertions    February 27, 2013

  • Best Paper Award

Complex protocol checks in Universal Verification Methodology Verification Components are often implemented using SystemVerilog Assertions; however, concurrent assertions are not allowed in SystemVerilog classes, so these assertions must be implemented in the only non-class based "object" available, the interface construct. This creates problems of encapsulation (since the verbose assertion code clutters the interface definition) and isolation (since the assertions depend on aspects of class configuration and operation). This paper demonstrates several pragmatic solutions for encapsulation and operation of assertions including mechanisms to make the assertions aware of the configuration and phases of the class-based verification environment.

( Mark Litterick )



DVCon 2013: Run-time Configuration of a Verification Environment - A Novel Use of the OVM/UVM Analysis Pattern    February 26, 2013

This paper describes a novel approach to modeling the real-time variation of delays required for the functional verification of a DIMM (Dual In-Line Memory Module) system consisting of DDR3 memory and other interface devices using an OVM environments analysis pattern to provide run-time delay control. The system requirements could not be verified without the ability to provide temporal control of the delay elements in the environment. Different approaches to solving this problem were examined before determining the solution adopted was the best fit for the task at hand.  ( Paul Marriott , Mark Ronan )


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DVCon 2013: Pragmatic Verification Reuse in a Vertical World    February 26, 2013

Successful application of block-level verification reuse improves the effectiveness of the top-level environment by providing additional checks, coverage and messages (and in some cases stimulus) which, as well as detecting more bugs, helps speed up debug for other system-level defects by providing improved internal visibility and enhanced bug isolation. Despite these benefits consistent efficient reuse is simply not being achieved in many companies. This paper revisits the vertical reuse problem from a fresh standpoint and addresses the fundamental issues involved, provides a comprehensive set of pragmatic reuse guidelines and also suggests how to go about retrofitting reuse to existing block-level environments.

( Mark Litterick )



DVCon 2013: OVM to UVM Migration - or There and Back Again, a Consultant's Tale    February 25, 2013

Tutorial 1: Lessons from the Trenches: Migrating Legacy Verification Environments to UVM™

  • http://videos.accellera.org/uvmmigrating/index.html

Many companies have a goal to migrate to UVM but this must be achieved without disrupting on-­‐going projects and environments. In our current clients we have all possible combinations of migration paths, a desire to move new projects to UVM and a definite need to support OVM for a good few years. This article presents an interesting OVM to UVM migration story where we successfully translated a whole family of verification components from OVM 2.1.2 to UVM, assessed the impact, and then reworked the original OVM code, which was still live in a series of ongoing derivative projects, to make the ongoing translations totally automatic and part of the project release mechanism.

( Mark Litterick )



MTV Austin: The Smartphone Approach to HVL Testbenches    December 11, 2012

This paper offers solutions, techniques and practices for verification engineers to allow those unfamiliar with HVL technologies to be able to use, fine tune, and debug their environments intuitively. ( Anders Nordstrom , Alex Melikian )



MTV Austin 2012: Yes We Kanban! Introducing an Agile Methodology to Manage Your Team    December 11, 2012

Kanban is a change management technique that can be adopted and adapted for many hardware development teams.  The key advantages of using Kanban are that it provides a visual overview of what your team is working on, identifies blocking issues and bottlenecks in your workflow, and creates opportunities for your team to proactively discuss and optimize their current processes.  This paper provides an overview of the Kanban methodology and provides some insight into how it can be incorporated into a typical hardware development team's existing management structure. ( Bryan Morris )


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MTV 2012: Getting Started with UVM    December 12, 2012

This presentation covers the basics of building a UVM testbench, creating stimulus, creating a register model, and interacting with legacy code. ( Vanessa Cooper )



SNUG Austin 2012: Verifying a Low Power Design    September 28, 2012

User expectations of mobile devices drive an endless race for improvements in both performance and battery life. This paper outlines the verification challenges created by some widely used low power design techniques, and shows how a digital verification methodology can be extended to existing testbenches, enabling low-power designs to be verified. ( Asif Jafri )



SNUG Austin 2012 Best Paper: Taming Testbench Timing - Time's Up for Clocking Block Confusion    September 28, 2012

The clocking block feature was designed to provide SystemVerilog verification environments with a versatile and well-structured way to access synchronous signals in a DUT or test harness. In practice, though, the use of clocking blocks has proved to be surprisingly error-prone, despite nearly a decade of application experience since they were first standardized.

This paper reviews the key features and purpose of clocking blocks and then examines why they continue to be a source of confusion and unexpected behavior for many verification engineers. Drawing from the authors’ project and mentoring experience, it highlights typical usage errors and how to avoid them. We clarify the internal behavior of clocking blocks to help engineers understand the reasons behind common problems, and show best-practice techniques that allow clocking blocks to be used productively and with confidence. Finally, we consider some areas that may cause portability problems and indicate how to avoid them.
( Kevin Johnston , Jonathan Bromley )



SNUG Ottawa 2012: UVM Sequence Item Based Error Injection    September 10, 2012

The proper testing of most digital designs requires that error conditions be stimulated to verify that the design either handles them in the expected fashion, or ignores them, but in all cases recovers gracefully.  A self-checking constrained-random environment can be put to the test when injecting errors, because unlike the device-under-test (DUT) which can potentially ignore an error, the testbench is required to recognize it, potentially classify it, and determine an appropriate response from the design.  In this paper we will present an error injection strategy using UVM that meets all of these requirements.  The strategy encompasses both active and reactive components, with code examples provided to illustrate the implementation details. ( Jeff Montesano , Mark Litterick )


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SNUG Europe 2012: I Spy with My VPI - Monitoring signals by name, for the UVM register package and more    May 20, 2012

UVM's register package has an "active monitoring" feature that allows you to predict the value of read-only status registers by probing the HDL signal that carries that status.  Until now, detecting value-changes on those status signals has been tricky, requiring hard-coded cross-module references that don't sit nicely with the configurability that we expect from a UVM test environment. This paper presents a novel SystemVerilog VPI/DPI package that cuts through this problem, allowing the signal's name to be specified as a string and removing all need for hard-coded references.  It's also great for monitoring other miscellaneous status signals in your UVM, OVM or VMM testbench, even if you're not using a register package.  We're already using this new package in our own projects.  Code, paper and presentation are all available for download here. ( Jonathan Bromley )



DVCon 2012: Getting Started with the UVM    February 27, 2012

Presented as part of the "UVM: Ready, Set, Deploy!" tutorial at DVCon 2012, this presentation discusses Vanessa Cooper's experiences with setting up a UVM testbench, including the configuration database, scoreboard, and register model. ( Vanessa Cooper )



DVCon 2012: A 30 Minute Project Makeover Using Continuous Integration    February 29, 2012

You've just spent a week working on a complex testbench change. You've regressed your changes and are ready to check them in. First, though, you pull in updates from other users and rerun regressions. Now you find that the testbench no longer compiles, or perhaps fails to run a basic test. You're late delivering your code and your manager is breathing down your neck. But it's not your fault! A Continuous Integration (CI) server can go a long way to preventing these situations. This paper describes the features and setup of one CI server (Jenkins) and how you can apply it to your design projects, with minimal effort. We consider both the technical and managerial challenges of using continuous integration. ( )



CDN Live EMEA 2011: FlexRayTM Conformance Testing using OVM    June 24, 2011

Presents a case study on how the Open Verification Methodology (OVM) was successfully applied to implement a SystemVerilog simulation-based conformance test environment for next generation FlexRayTM 3.0 Automotive Communications System controllers.

( Mark Litterick )


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User2User 2010: Simulation-Based FlexRayTM Conformance Testing - an OVM Success Story    June 22, 2011

Presents a case study on how the Open Verification Methodology (OVM) was successfully applied to implement a SystemVerilog simulation-based conformance test environment for next generation FlexRayTM 3.0 Communications System controllers. ( Mark Litterick )



EDA Tech Forum 2010: Simulation-Based FlexRayTM Conformance Testing using OVM    June 21, 2011

This is the case study on how the OVM was used to implement a SystemVerilog simulation-based conformance test environment for next generation FlexRayTM 3.0 Automotive Communications System controllers.

 ( Mark Litterick )



Verification Horizons June 2010: Simulation-Based FlexRayTM Conformance Testing - an OVM Success Story    June 20, 2011

This article presents a case study on how the Open Verification Methodology (OVM) was successfully applied to implement a SystemVerilog simulation-based conformance test environment for next generation FlexRayTM 3.0 Communications System controllers. ( Mark Litterick )



SNUG 2010: Interoperable Testbenches Using VMM TLM    April 13, 2010

SOC’s are getting larger all the time and so is the challenge to verify these designs in a short period of time. This paper presents a transaction level-based methodology in the VMM to stan-dardize development of various pieces of a verification environment and the communication be-tween them. This methodology promotes reuse and helps integrate modules from various sources to interact together seamlessly.


This paper received a technical committee honorable mention award at SNUG 2010.
( Asif Jafri , Nasib Naser [Synopsys] )


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SNUG 2010: Integrating e Verification IP in a VMM Testbench    April 12, 2010

Modern testbenches often consist of components drawn from multiple languages. In many of these cases, multi-language and multi-methodology interaction is not well defined. In this paper, we will demonstrate the use of e verification components (eVCs) in a SystemVerilog/VMM testbench. Several complex issues arise when using SystemVerilog as the ‽primary” language. Initial simulator engine synchronization, random generation ordering, timing problems caused by program blocks, and methodology synchronization between the VMM and eRM will all be discussed. ( )



DVCon 2010: Stimulating Scenarios in the OVM and VMM    April 12, 2010

In this paper, advanced stimulus generation concepts, architecture, and motivation will be described. Tips for a successful stimulus generation implementation will be provided, and solutions from the VMM and OVM libraries will be compared and contrasted. ( Scott Roland )



SNUG 2009: Using the New Features in VMM 1.1 for Multi-Stream Scenarios    April 18, 2009

Today's verification solutions often require complex concurrent streams of stimulus controlled from higher level transactors or scenarios. The VMM 1.1 library has been enhanced to add this capability, and support the management of access to the resources shared by different stimulus streams, i.e. multiple streams providing stimulus to the same transactor. This paper describes the challenges faced in developing these new features, and takes a detailed look at how they are used in a VMM "multi-stream scenario" environment.


Honorable Mention - Technical Committee Award: SNUG San Jose 2009
( Jason Sprott , Sumit Dhamanwala, Cliff Cummings )



OCP-IP Article 2008 - OCP Profiles and Transactions    January 5, 2009

Published in the DEC 2008, Vol 7 edition of the OCP-IP Newsletter (http://www.ocpip.org/)
This article demonstrates how two key aspects of OCP "profiles and transactions" were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems. The article uses the Verilab OCP uVC as an example. This uVC is a mixed-language OCP compliant verification component that supports a major subset of Open Core Protocol Specification 2.2. ( Mark Litterick )


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SNUG 2008: Multi-Stream Scenarios - Enhancing Stimulus Generation in the VMM    October 7, 2008

Boston SNUG2008 (Presentation Only). Takes a look at the new Multi-Stream Scenario features Verilab developed for Synopsys, to upgrade the VMM's capabilities. These features are scheduled to be released in VMM 1.1.
( Jason Sprott , Sumit Dhamanwala )



SVUG 2008: Improve Your SystemVerilog OOP Skills by Learning Principles and Patterns    October 7, 2008

SVUG2008 Fall presentation. This presentation looks at how you can improve your object-oriented programming skills by exploiting the wisdom of others. We introduce some key object-oriented design principles and look at what design patterns bring to the party. ( Jason Sprott )



ClubT 2008: Intro to Requirements Based Verification    October 7, 2008

A short overview of Requirements Based Verification as presented at ClubT 2008 in Bristol. ( David Robinson )

  • PDF (2.04 MB)


White Paper 2008: Endian - From the Ground Up    August 18, 2008

This document explores endianness using a coordinate system terminology, and explains common endian misconceptions as arising from coordinate system ambiguity. Topics covered are: The definition and properties of endian; the endian problem; independence of bit and byte endian; why bit significance and byte address must be managed in hardware; why byte significance must be managed in software. ( Kevin Johnston )


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DAC 2008: The Myth of SystemVerilog Interoperability    July 30, 2008

In this 45 minute presentation first given at DAC 2008, JL Gray, member of the Accellera VIP TSC and author of Cool Verification (www.coolverification.com) looks at the verification interoperability problem by examining SystemVerilog interoperability between simulators and functional differences between competing methodology libraries.  JL will also discuss the likelihood SystemVerilog interoperability will move (unlike Santa and the Tooth Fairy) from myth to reality as a result of the efforts of the Accellera VIP TSC.



DAC 2008: Getting Started with Requirements Based Verification    June 17, 2008

Verification planning is an essential part of the chip design process, yet experience shows that it is seldom attempted with any rigor.  Enthusiasm for the task tails off rapidly as soon as the "real work" of coding the testbench becomes feasible.  Limited knowledge of how to do effective verification planning, low personal motivation and benefits, and lack of permission are common reasons for abandoning the planning early. Subsequent verification tends to be inefficient, impacting both the quality of the design and delivery schedule, and leading to a stressful and unsatisfying project experience for all involved.

In this one hour presentation first given at DAC 2008 in Anaheim, California, Dr. David Robinson from Verilab provides an introduction to Requirements Based Verification, a verification planning approach which aims for efficiency by allowing project stakeholders visibility into the size, scope, progress and risk of the overall verification process. Good risk-based visibility at all stages helps ensure that verification proceeds with few surprises.

This presentation is extracted from Verilab's Requirements Based Verification review process, and covers the following topics:

  • Requirements Based Verification overview
  • How to create good requirements
  • Risk based prioritization

The presentation will be of interest to verification engineers and managers who would like to improve the efficiency of their verification efforts.

( David Robinson )



SVUG 2007: Functional Coverage in SystemVerilog    October 9, 2007

SVUG 2007 Presentation on Functional Coverage in SystemVerilog, comparing covergroups and cover properties, and some tips on coding for analysis. ( Jason Sprott )



SVUG 2007: Assertion-Based Verification using SystemVerilog    October 8, 2007

Overview of ABV using SystemVerilog Assertions, including: general syntax and components, formal arguments, local variables, multiple clocks
Detailed analysis of complex worked examples, including: combinations of SVA constructs, demonstrate capability of SVA ( Mark Litterick )


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Application Note 2006: FPGA Protoyping in Verification Flows    December 8, 2006

Hardware-assisted verification environments often make use of FPGAs to prototype the
ASIC in order to provide a faster alternative to simulation and allow software development to proceed in parallel with hardware design. This application note addresses the factors that should be taken into account in such a flow in order to maximize the effectiveness of the overall verification environment. ( Mark Litterick )



White Paper 2006: An Introduction to Aspect Oriented Programming in e    June 21, 2006

White Paper 2006 ( David Robinson )



CDN Live 2006: Simplify SoC Verification using a Generic Approach    June 1, 2006

CDNLive! June 2006, Nice, France ( David Robinson )



NMI 2006: Simplify SoC Verification using a Generic Approach    February 1, 2006

NMI Verification Network Event Feb. 2006 ( David Robinson )


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DVCon 2006: Using SystemVerilog Assertions in Gate-Level Verification Environments    February 1, 2006

Real-world requirements such as multiple clock domains and low-power modes of operation, including frequency and voltage scaling, often necessitate gate-level System-on-Chip (SoC) verification environments to complement the standard RTL based simulations. If the verification environment relies on assertion-based checkers to validate grey-box operation then gate-level simulations will also benefit from reuse of these assertions. This paper provides an overview of the problems related to gate-level timing and connectivity with a focus on how these affect the operation of the SVA code. A methodology is presented that enables reliable operation and reuse of the SVA in simulation environments that support RTL and gate-level implementations of the device- under-test. The paper also discusses SVA timing checks that can be added to the gate-level environment to improve checking and coverage. 

( Mark Litterick )



DVCon 2006: Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions    February 1, 2006

  • Best Paper Award

Recent advances in automated formal solutions for verification of clock domain crossing signals go far towards reducing the risk of clock related defects in multi-clock system-on-chip devices. However the vast majority of multiple clock-domain devices still utilize a flow which does not involve these specialized tools or formal verification techniques. This paper presents a pragmatic alternative methodology, using SystemVerilog Assertions in a simulation-based verification flow, to validate the correct operation and use of synchronizers while emulating the effects of CDC jitter in order to stress the functional operation of the rest of the device. 

( Mark Litterick )



White Paper 2005: Shorten and Simplify SoC Verification using a Generic eVC    November 1, 2005

White Paper ( David Robinson )



Mentor Solutions Expo 2005: Focusing Assertion Based Verification Effort for Best Results    November 1, 2005

This presentation demonstrates how to target SystemVerilog assertions for maximum effectiiveness and return on effort. Practical examples are provided taken from a real project together with an overview of project results. Mentor Graphics Solutions Expo Scotland 2005. ( Mark Litterick )


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ClubV 2005: Verifying In-situ Embedded Software Using Coverage Driven Verification    October 1, 2005

Verisity ClubV 2005 ( David Robinson )



DAC 2005: Using SystemVerilog Assertions for Functional Coverage    July 1, 2005

SystemVerilog Assertions (SVA) can be used to implement relatively complex functional coverage models under appropriate circumstances. This paper explores the issues and implementation of such a functional coverage model to demonstrate both the capabilities of SVA coverage and illustrate coding techniques which can also be applied to the more typical use of SVA coverage, which is to specify key corner cases for the RTL from the designer’s detailed knowledge of the structural implementation. This paper is related to previous work published at SNUG Europe 2005 called Utilizing Vera Functional Coverage in the Verification of a Protocol Engine for the FlexRayTM Automotive Communication System; readers are encouraged to read both papers. DAC 2005 (white paper presented on Accellera booth).

( Mark Litterick )



SNUG Europe 2005: Utilizing Vera Functional Coverage in the Verification of a Protocol Engine for the FlexRay(TM) Automotive Communication Sytem    May 1, 2005

The FlexRayTM communication system for advanced automotive control applications such as drive-by-wire is specified at a micro-architectural level using graphical Specification and Description Language (SDL) representations for the main protocol engine operation. Verifying that a specific implementation conforms to this specification requires close attention to all possible state transitions and conditional paths, for a potentially huge variety of node and cluster configurations. This paper explores the issues involved with measuring and managing the functional coverage for a FlexRayTM controller using Vera. Practical solutions and code examples are presented based on the verification environment for a FlexRayTM protocol engine implementation at Freescale Semiconductor. 

( Mark Litterick , Marcus Brenner - Freescale Semiconductor )



DATE 2005: An Assembler Driven Verification Methodology (ADVM)    April 1, 2005

Date 2005 ( John MacBeth , Ken Gray , Dietmar Heinz - Infineon Technologies AG )


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SNUG Europe 2004: Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments    January 1, 2005

Real world requirements such as low-power modes of operation and multiple clock domains often necessitate gate-level System-on-Chip (SoC) verification environments. Additional complexities introduced by tester compliance impose restrictions on the control and repeatability of simulations over all situations, including register-transfer-level (RTL) and different gate-level conditions. Making full use of the Vera high-level verification language in these circumstances requires special considerations and techniques not normally applied in a module-level RTL testbench. If the intent is to reuse Vera monitors, drivers and result- checkers in the gate-level SoC environment then the code must be designed appropriately. This paper first explores the generic issues of interacting with a gate-level SoC in a tester compliant manner and then proceeds to derive Vera coding guidelines that ensure robust operation across a range of testbench abstractions from module-level RTL through to tester- compliant gate-level SoC implementations. 

( Mark Litterick )



MTV 2004: Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments    January 1, 2005

Real world requirements such as low-power modes of operation and multiple clock domains often necessitate gate-level System-on-Chip (SoC) verification environments. Additional complexities introduced by tester compliance impose restrictions on the control and repeatability of simulations over all situations, including register-transfer-level (RTL) and different gate-level conditions. Making full use of the Vera high-level verification language in these circumstances requires special considerations and techniques not normally applied in a module-level RTL testbench. If the intent is to reuse Vera monitors, drivers and result-checkers in the gate-level SoC environment then the code must be designed appropriately. This paper first explores the generic issues of interacting with a gate-level SoC in a tester compliant manner and then proceeds to derive Vera coding guidelines that ensure robust operation across a range of testbench abstractions from module-level RTL through to tester-compliant gate- level SoC implementations. 

( Mark Litterick , Joachim Geishauser - Motorola GmbH )



SNUG Europe 2004: Learn to do Verification [in Vera] with AOP? We've just learned OOP!    January 1, 2005

SNUG Europe 2004 ( David Robinson )



SNUG Europe 2003: A Scalable Method of Propagating Event Messages Throughout a Vera Testbench    January 1, 2005

SNUG Europe 2003 ( David Robinson )


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Mentor Designer's Forum 2002: FPGA-Centric Functional Verification    May 22, 2002

This presentation addresses the requirements for verification of complex FPGAs using a mixture of simulation and design-for-verification approaches to establish correctness of the complex control-based functionality allowing for on-the-bench testing of full operational modes, data and traffic throughput. The targeting of key features for different stages in the process is discussed along with the need for repeatable regression results in both simulation and bench-based testing. Mentor Graphics Scotland and Ireland Designers Forum 2002.
( Mark Litterick )


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