Verilab Promotes JL Gray to Vice President
March 30, 2010  

Verilab Promotes JL Gray to Vice President to Assist in Management of Continuing International Growth

AUSTIN, TX, March 30, 2010 -- Verilab Ltd., the team of international VLSI verification experts, has promoted JL Gray to the position of vice president, reporting directly to chief executive officer, Tommy Kelly. Along with the existing executive team, JL will assist in the overall management and development of Verilab in its ongoing international growth.

Since joining Verilab in 2004, JL has developed a consulting practice in verification planning, methodology development, and project execution with a wide range of clients in Europe, Asia, the Middle East, and the US. JL has presented workshops on verification methodology and planning around the world. He also has implemented verification environments in all of the major e and SystemVerilog libraries (eRM, VMM, and OVM). In addition to his consulting activities, JL has contributed to the EDA industry as Verilab's representative on the Accellera Verification IP Technical Subcommittee.

 JL is well known in the electronic design automation (EDA) industry as the author of "Cool Verification", a blog about hardware verification from a consultant's perspective. He has also worked extensively on the application of social media to the EDA industry as a means of fostering collaboration in the wider engineering community. JL has a BSEE from Purdue University in West Lafayette, Indiana.

"JL has contributed greatly to our growth and to the industry over the past five years", said Tommy Kelly, Verilab's CEO. "The market is increasingly recognizing the challenges of functional verification in VLSI, and we are excited to have JL join the international management team as Verilab continues to grow its capabilities to help clients meet those challenges".

JL Gray will be presenting a paper on "Integrating eVCs in a VMM Testbench" at SNUG in San Jose on Tuesday, March 30^th from 1:00-2:30. For more information, please see http://www.synopsys.com/Community/SNUG/SanJose/Pages/Abstracts.aspx?loc=San+Jose&locy=2010#TB2.

About Verilab

Verilab Ltd. is a design verification company providing engineering and consulting services and training in the verification of complex systems-on-chip (SoCs), ASICs, and FPGA designs. Verilab experts specialize in solving the toughest problems in VLSI functional verification, from chip rescue and critical path pruning, through sophisticated verification IP development, to complete methodology re-engineering. Established in 2000, the company serves clients across Europe and the USA from sites in Austin, Munich, Bristol and Glasgow. For additional information, see www.verilab.com

All trademarks or registered trademarks mentioned in this release are the intellectual property of their respective

# # #

Note to editors:

A photo of JL Gray is available upon request

Editorial Contact:

Cayenne Communication LLC

Michelle Clancy, +1-252-940-0981, michelle.clancy@cayennecom.com