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Verilab at SNUG Canada 2015

September 30, 2015 by Paul Marriott

Verilab will be participating in SNUG Canada on Thursday 1st October.

Bryan Morris will re-present his paper entitled “RESSL UVM Sequences to the Mat” that he co-authored with Jeff McNeal (which won the 2014 SNUG SV Technical Committee’s Best Paper award) in the A1 - User Session - Testbench Techniques with UVM session.

Alex Melikian will present his paper, co-authored with Hilmar Van Der Kooij and entitled “Replacing Hardcoded Register Values with Hardcore Abstraction” in the same session.

Bryan and Alex will be available to discuss their papers at the SNUG Pub following the end of the afternoon’s technical sessions.

[updated: Alex and Hilmar's paper and slides can be found on our resources page. ]

Verilab at SNUG Austin 2015

September 17, 2015 by Paul Marriott

Verilab will be at the Designer Community Expo where we will be raffling an Amazon Echo.

On Friday September 18th, Kevin Johnson will be presenting in the FA3 Verification - Improving Test Generation session a paper co-authored with Jonathan Bromley entitled Is Your Testing N-Wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus.

Jeff Montesano will be presenting the Technical Committee Award Winner during the FB4 User & Tutorial Session - UVM Agents, Verdi Debug session a paper co-authored with Mark Litterick entitled Mastering Reactive Slaves in UVM.

Papers and presentations for both can be downloaded from the Papers and Presentations section of our website.

Thoughts on Verification: Doing Our Work in Regulated Industries

August 18, 2015 by Alex Melikian

In this edition of “Thoughts on Verification”, Verilab consultant Jeff Montesano interviews fellow consultant Jeff Vance on verification in regulated industries. Jeff Vance has extensive verification experience in the regulated nuclear equipment industry. The discussion explains the role of regulators and how it can affect verification processes as well as interactions within the team. They also discuss the challenges and how innovation manifests in such an industry.

Jeff Montesano: Hi, everyone. Welcome to another edition of Thoughts on Verification. I’m pleased to have my colleague, Jeff Vance here with me to discuss his experience in working in regulated industries and how it would impact verification. Jeff, thanks for joining me.

Jeff Vance: Thanks. Happy to be here.

JM: So let’s talk a little bit about what would you think are the primary differences between working in regulated industries, such as nuclear and military, versus unregulated industries, where you’re making commercial products that might be going into cell phones and things like that.

JV: Yes. My experience is mostly in the nuclear industry, working on safety critical systems for the automation of nuclear power plants. There are a lot of differences working in that domain compared to most non-regulated industries. The biggest difference is you have a regulator such as the Nuclear Regulatory Commission (NRC) who has to approve the work you’re doing. So there’s a huge change to priorities. There’s a change to the daily work that you do, the mindset of the people and how the work is done. Ultimately, it’s not enough just to design your product and catch all your bugs. You have to prove to a regulator that you designed the correct thing, that it does what it’s supposed to do, and that you followed the correct process.

JM: I see, I believe we’ve covered something like this before with the aerospace industry. So you said there’s a difference in priorities, can you give me an example of what types of priorities would be different?

JV: I think the biggest difference is that you must define a process and prove that you followed it. That’s how you prove that the design has no defects. So even if you designed the perfect product and the verification team found all the bugs; there will still be an audit. They’re going to challenge you, and you’re going to have to prove that everything you did is correct. The primary way to do this is to define a process that the regulator agrees is good and create a lot of documentation that demonstrates you followed it. If you can prove that you followed that process throughout the entire life cycle of the product, that demonstrates to an auditor that your design is correct and can be used.

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Extending the e Language with Anonymous Methods

July 13, 2015 by Paul Marriott

Many programming languages like Python, Perl, and Ruby support anonymous methods, typically through classes or other constructs representing a block of code. These are useful to construct code by a higher-order method or to be used as arguments by higher-order methods.

The e language knows code blocks in (for example) list pseudo-methods and macro definitions, but they are defined statically and cannot be referenced, unlike the aforementioned languages. Using reflection, template structs, and define-as-computed macros, we implemented anonymous methods functionality in the e language, modeled after the corresponding Ruby feature.

It is licensed under Apache 2.0 and available in the vlab_util package.

The full article, written by our consultant Thorsten Dworzak, is published on the Cadence blog here:

http://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/07/10/extending-the-e-language-with-anonymous-methods

See http://www.verilab.com/resources/other-downloads/ for download information.

Thoughts on Verification: svlib - Including the Batteries for SystemVerilog (part 2)

June 18, 2015 by Alex Melikian

In part 2, Alex and Jonathan continue covering features in svlib. In addition, they also cover how someone in the verification community can quickly ramp-up, request support for problems and get involved with svlib. Part 1 can be viewed here.

Alex Melikian: Another feature set offered by svlib in addition to what we’ve talked about so far, would be its functions related to the operating system. Once again, the standard SystemVerilog already offers some functionality interacting with the OS, but svlib takes it a level further. Can you tell us what svlib can do in this respect that SystemVerilog does not?

Jonathan Bromley: I can’t imagine a general-purpose programming language that doesn’t have library or built-in features for figuring out the time of day, discovering the values of environment variables, exploring the filesystem’s directory structure and so forth. We should expect that to be available, without fuss, in SystemVerilog - but, frustratingly, it is not. That’s precisely what svlib’s OS interaction features are intended to offer. There’s a collection of related sets of features - they’re distinct, but in practice you’ll probably use them together.

First, there’s a set of tools (implemented in the Pathname class) that allow you to manipulate Linux file and directory names in a convenient and robust way. If you try to do that as a simple string processing task, you’ll typically get some nasty surprises with things like doubled-up path separators (slashes); the Pathname class copes with all of that. Next, there’s a slew of functions for inquiring about the existence and state of files, mostly based on the “stat” system call that you may be familiar with. You can check whether a file exists, decide if it’s a directory or softlink, find whether you have write permission on it, and examine its creation and modification datestamp. You can also find what files exist at any given location, using the same “glob” syntax (star and query wildcards) that’s familiar to anyone who has used the “ls” command.
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Thoughts on Verification: svlib - Including the Batteries for SystemVerilog (part 1)

June 10, 2015 by Alex Melikian

In this edition of “Thoughts on Verification”, Verilab consultant Alex Melikian interviews colleague Jonathan Bromley, lead author of the svlib library. svlib is a free open source utility functions library for SystemVerilog, available on Verilab’s website.

In part 1, Alex and Jonathan begin the discussion by covering why svlib was created, features it offers, as well as some of the internal details of this open source library.

Alex Melikian: Hi Jonathan! It’s great to have you with us. I believe you’re our first ‘repeat’ interviewee on these ‘Thoughts on Verification’ series, so I should really be saying ‘welcome back’.

Jonathan Bromley: Thanks, Alex! I’m sure you could have found someone more exciting from among our amazing colleagues, but it’s a pleasure to be back in the hot seat.

AM: We’re here to discuss svlib, an ongoing project you’ve been working for some time now. Let’s begin by introducing it for the unfamiliar, how would you best describe svlib?

JB: It’s partly a “pet project” that I’ve been thinking about for some years, and partly a response to genuine needs that I’ve encountered - not only in my own verification work with SystemVerilog, but also when observing what our clients ask for, and what I heard from students back when I was delivering training classes before joining Verilab. It’s a package of general-purpose library functions covering string manipulation, regular-expression processing, file access and operating-system interface stuff such as wall-clock time and directory exploration, and a bunch of other utility functions. Almost all are things that - frustratingly - aren’t available in standard out-of-the-box SystemVerilog, but exist in just about any general-purpose language. With svlib added to your toolkit, SystemVerilog starts to look a lot more like a competent all-round programming language.

Most of the non-trivial functionality in svlib is implemented using SystemVerilog’s fantastic C-language interfaces, the DPI and VPI. For many years, folk who are expert in both SystemVerilog and C/C++ have used those interfaces to implement their own additional functionality. The contribution of svlib, I hope, is to make a wide range of useful new features freely accessible to anyone who’s familiar with SystemVerilog. No C or DPI expertise is needed to use it.

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Verilab at 52nd DAC

June 4, 2015 by Paul Marriott

Verilab’s CTO, Jason Sprott will be giving a presentation co-authored with Cadence’s John Brennan entitled Predicting Verification Closure of IP Designs.

Jason will be in Room 101 at 52nd DAC next Tuesday June 9th presenting about how verification closure of IP designs can be both predictable and deterministic. Harnessing the power of big data, a prediction engine will be described which allows metadata from previous projects to be used to forecast all the key metrics for the current project.

Follow us on twitter @verilab

SystemVerilog and UVM Training in Austin, Apr 20-24 2015

April 16, 2015 by Paul Marriott

Sunburst Design and Verilab have joined forces to provide what we think is a pretty unique training opportunity to be held in Austin (TX) next week.

Over two courses and five days, from April 20-24, we’ll deliver a hybrid training course, covering the core fundamentals needed to master SystemVerilog and UVM, augmented with up-to-date real-industry application experiences. It will be suitable for beginners in SV, but also for people with up 2 years’ experience with the language.

The training will be delivered by SystemVerilog guru Cliff Cummings, and Verilab Fellow and co-founder, Mark Litterick, who presented an Advanced UVM Tutorial at DVCon Europe 2014.

For more information and registration instructions see: www.sunburst-design.com/systemverilog_training_schedule

Follow us on twitter @verilab

SNUG-SV 2015 Wrap Up

April 3, 2015 by Paul Marriott

Verilab consultant Jeff McNeal presented a paper he co-authored with Bryan Morris entitled “RESSL UVM Sequences to the Mat”.

A copy of the paper, presentation and source-code is available on our website under the Papers and Presentations category of the resources section.

Happy Birthday to Verilab

April 1, 2015 by Paul Marriott

Verilab co-founder and CEO  Tommy Kelly writes:

Today’s date is not necessarily the best on which to make any kind of announcement, and it’s true that the complexity of growing an international business from a standing start can often feel like an April’s Fool joke, especially when I consider all the silly government-induced things we need to put up with. But it’s true; Verilab is fifteen years old today!

Read the full article here

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