Scott Roland

It is with great sadness that we announce the passing of our friend and colleague Scott Roland. He died on April 2nd, 2017, surrounded by his family and friends, following complications in battling a recent illness.

Born in the United States, and a graduate of Brown University Computer Science, Scott was an accomplished chip design and verification engineer. By 2007, his work had already taken him to Switzerland from where he then moved to Germany to join the Verilab Munich team in January 2008. As a consultant, Scott was a key contributor to a range of important chip projects across Europe, his work taking him to clients not only in Germany, but also Ireland, Sweden, Scotland, and Austria. A specialist in the complex computing infrastructures that underpin modern chip design efforts, Scott made significant improvements in the use of version control and build automation systems in all of the projects on which he worked, saving his teams many weeks and months of valuable design cycle time.

In addition, Scott brought the ingenuity of the “born engineer” to all aspects of his work be it in rooting out deep design bugs, fixing bugs in the design and verification tools themselves, or even as far as helping decide on the correct font for editing code, a decision of such importance that wars have been started for less. Perhaps the best example of Scott’s combination of attention to detail and MacGyver-like inventiveness was in his design of a standing desk. Clearly having been influenced by German frugality, Scott avoided the expense of buying a ready-made system and instead acquired some cinder blocks and used those to raise his existing desk a few feet.

A Swabian thriftiness was not the only aspect of his adopted home’s culture that Scott and his wife Julie acquired. Keen observers of, and participants in, the cultures of all the countries in which they spent time, Scott and Julie took the German posting as an opportunity to enthusiastically embrace all things Bavarian. He wore his lederhosen with pride —especially at Oktoberfest—with Julie completing the picture resplendent in traditional dirndl. Then shortly after moving to the Verilab Edinburgh office in November 2012, he dived straight into the Scottish scene by attending a Burns Night supper at a colleague’s house. Perhaps it was a little bit too much culture too quickly though, because he was heard to comment, amid the sound of bagpipes, that, “Mercifully Yammer [Verilab's internet messaging tool of choice] doesn’t do audio!”

Scott Roland - August 2016

Scott is survived by Julie, an accomplished artist living in Edinburgh. Julie took this picture of him, commenting, “This photo is one of my favorites. It was taken back in August. Scott was in the middle of receiving his second round of chemo at the hospital in Edinburgh. He felt so well that we passed on hospital lunch and went out to eat at a local pub instead.’‘

Verilab is proud to have senior consultant Jonathan Bromley host the “SystemVerilog Jinxed Half My Career” panel at DVCon 2017, on Wednesday March 1st. Jonathan continues to serve on the SystemVerilog IEEE committee and is the author of numerous papers, including the recently published “Slicing Through the UVM’s Red Tape”. We took a moment with Jonathan to preview what this panel will cover and what those planning or thinking of attending should expect.

The title is “SystemVerilog Jinxed Half My Career : Where do we go from here”, which signals this panel will focus on areas of improvement. What are those areas of frustration in SystemVerilog you feel need improvement?

It would be easy to give a “where do I start?” response, and it’s not difficult to come up with a laundry list of desirable SystemVerilog improvements and nit-picky complaints. But this is DVCon, and our very knowledgeable and sophisticated audience deserves better. We have five extraordinarily experienced panelists and I hope we can venture beyond details of the languages and tools we have today, and think creatively about what we can and should hope for in the mid-term future. Many languages have been used successfully to create advanced testbenches - ‘e’, C++, Python, Vlang - but there’s no question that SystemVerilog remains dominant. Why is that? What sort of code will verification engineers be writing in five, ten years’ time?
(more…)

Jonathan Bromley and Jason Sprott will be delivering a tutorial on Wednesday 19th October 10:00-11:30AM at DVCon Europe 2016 in Munich.

We find that getting started on formal verification can be a challenge. It’s different to traditional simulation, with some unfamiliar concepts. However, for the right kind of problem, it’s just too good to miss out on due to the lack of experience. This tutorial aims to address that initial lack of confidence and basic knowledge, helping engineers to get started on real project work using formal verification. We’ll be using a small case study to take attendees through the lifecycle of a formal verification project for a block-level RTL design.

A full description of the tutorial is detailed in the DVCon Europe 2016 conference program

Jeff Montesano and Jeff Vance presented their paper entitled “Configuring a Date with a Model – A Guide to Configuration Objects and Register Models” at SNUG Austin this past September 2016.

The full paper and presentation slide can be downloaded from our resources section: snug2016model.

Jonathan Bromley, Mark Litterick, and Vanessa Cooper’s paper entitled “Effective SystemVerilog Functional Coverage: design and coding recommendations” can also be downloaded from our resources section: snug2016cover. Unfortunately, Vanessa was unable to present this due to sickness, though this paper did win the Technical Committee Honourable Mention Award at SNUG2016UK.

Thanks to all who attended!

All of our papers and presentations can be downloaded from our resources page’s papers-and-presentations section.

We’re proud to announce Verilab consultants Jeff Montesano, Jeff Vance and Vanessa Cooper will be presenting at SNUG Austin 2016 this Thursday September 29^th.

Jeff Montesano and Jeff Vance will present “Configuring a Date with a Model – A Guide to Configuration Objects and Register Models” in the morning session. In addition, as conference technical chair, J. Montesano will have the pleasure to give a short address and introduce the morning keynote speakers.

Vanessa Cooper will present “Effective SystemVerilog Functional Coverage: Design and Coding Recommendations” in the afternoon session.

For more information on times and events consult the schedule, or download the “SNUG Austin” mobile app.

We look forward to seeing you there and hear what you have to say about verification.

In part 2, Alex and Jonathan continue covering features in svlib. In addition, they also cover how someone in the verification community can quickly ramp-up, request support for problems and get involved with svlib. Part 1 can be viewed here.

Alex Melikian: Another feature set offered by svlib in addition to what we’ve talked about so far, would be its functions related to the operating system. Once again, the standard SystemVerilog already offers some functionality interacting with the OS, but svlib takes it a level further. Can you tell us what svlib can do in this respect that SystemVerilog does not?

Jonathan Bromley: I can’t imagine a general-purpose programming language that doesn’t have library or built-in features for figuring out the time of day, discovering the values of environment variables, exploring the filesystem’s directory structure and so forth. We should expect that to be available, without fuss, in SystemVerilog - but, frustratingly, it is not. That’s precisely what svlib’s OS interaction features are intended to offer. There’s a collection of related sets of features - they’re distinct, but in practice you’ll probably use them together.

First, there’s a set of tools (implemented in the Pathname class) that allow you to manipulate Linux file and directory names in a convenient and robust way. If you try to do that as a simple string processing task, you’ll typically get some nasty surprises with things like doubled-up path separators (slashes); the Pathname class copes with all of that. Next, there’s a slew of functions for inquiring about the existence and state of files, mostly based on the “stat” system call that you may be familiar with. You can check whether a file exists, decide if it’s a directory or softlink, find whether you have write permission on it, and examine its creation and modification datestamp. You can also find what files exist at any given location, using the same “glob” syntax (star and query wildcards) that’s familiar to anyone who has used the “ls” command.
(more…)

In this edition of “Thoughts on Verification”, Verilab consultant Alex Melikian interviews colleague Jonathan Bromley, lead author of the svlib library. svlib is a free open source utility functions library for SystemVerilog, available on Verilab’s website.

In part 1, Alex and Jonathan begin the discussion by covering why svlib was created, features it offers, as well as some of the internal details of this open source library.

Alex Melikian: Hi Jonathan! It’s great to have you with us. I believe you’re our first ‘repeat’ interviewee on these ‘Thoughts on Verification’ series, so I should really be saying ‘welcome back’.

Jonathan Bromley: Thanks, Alex! I’m sure you could have found someone more exciting from among our amazing colleagues, but it’s a pleasure to be back in the hot seat.

AM: We’re here to discuss svlib, an ongoing project you’ve been working for some time now. Let’s begin by introducing it for the unfamiliar, how would you best describe svlib?

JB: It’s partly a “pet project” that I’ve been thinking about for some years, and partly a response to genuine needs that I’ve encountered - not only in my own verification work with SystemVerilog, but also when observing what our clients ask for, and what I heard from students back when I was delivering training classes before joining Verilab. It’s a package of general-purpose library functions covering string manipulation, regular-expression processing, file access and operating-system interface stuff such as wall-clock time and directory exploration, and a bunch of other utility functions. Almost all are things that - frustratingly - aren’t available in standard out-of-the-box SystemVerilog, but exist in just about any general-purpose language. With svlib added to your toolkit, SystemVerilog starts to look a lot more like a competent all-round programming language.

Most of the non-trivial functionality in svlib is implemented using SystemVerilog’s fantastic C-language interfaces, the DPI and VPI. For many years, folk who are expert in both SystemVerilog and C/C++ have used those interfaces to implement their own additional functionality. The contribution of svlib, I hope, is to make a wide range of useful new features freely accessible to anyone who’s familiar with SystemVerilog. No C or DPI expertise is needed to use it.

(more…)

Verilab’s CTO, Jason Sprott will be giving a presentation co-authored with Cadence’s John Brennan entitled Predicting Verification Closure of IP Designs.

Jason will be in Room 101 at 52nd DAC next Tuesday June 9^th presenting about how verification closure of IP designs can be both predictable and deterministic. Harnessing the power of big data, a prediction engine will be described which allows metadata from previous projects to be used to forecast all the key metrics for the current project.

Follow us on twitter @verilab

Paul Marriott and Jonathan Bromley won the SNUG2014-SiliconValley’s Technical Program Committee Best Paper award for their paper entitled “Reverse Gear: Re-imagining Randomization Using the VCS Constraint Solver”. Unable to attend the conference in person, Paul was ably represented by Bryan Morris who presented the paper to an audience of around 250 people.

The full paper can be downloaded here: “Reverse Gear” - Re-imagining Randomization with the VCS Constraint Solver (PDF) and the slides can be downloaded here: Presentation (PDF)

The code used in the examples can be downloaded here: vlab_SNUG_2014.tar.gz

Jonathan will be presenting the paper at the C4 session of SNUG UK on Thursday 22nd May and then at the A5 track of SNUG Munich on Tuesday May 27th.

Verilab have added their OCP uVC verification component to the OCP-IP Library.

The Verilab OCP uVC is a mixed language verification component for the Open Core Protocol (OCP) implemented using SystemVerilog and e verification languages. It can be used as an Open Verification Methodology (OVM) Verification Component (OVC) in SystemVerilog-only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular e Verification Component (eVC).

The datasheet for the OCP uVC can be downloaded here