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Archive for the ‘SystemVerilog’ Category

DAC 2008 Presentations Now Posted

Wednesday, July 30th, 2008 by JL Gray

Just a quick FYI… both David Robinson and I have posted our DAC presentations on Verification Planning and SystemVerilog Interoperability on the Verilab website. Please check them out and let us know if you have any questions or comments!

SystemVerilog Gotcha: (when copying) a struct is not a class by another name

Sunday, January 20th, 2008 by Jason Sprott

SystemVerilog has two “similar” data types that allow variables to be grouped together in a handy package: the struct and the class. I’ve heard it often said, when explaining what a class (an object-oriented data type) is, that it is just like a C struct with functions. I used to have no problem with that, until, when reviewing and debugging testbench code, I started seeing some problems related to the way classes have to be treated differently to structs. One of the most common errors I’ve found is when data structures composed of classes are copied.

Consider the following: (more…)

SystemVerilog User Group 2007 Fall Meeting Stats

Wednesday, November 7th, 2007 by Jason Sprott

SVUG started in March 2007 and has had a total of 8 meetings so far. It’s been a great first year for all of us involved with SVUG. The meetings and forum have been met with real enthusiasm. We’ve had some interesting technical discussions with new and experienced developers using SystemVerilog on their projects. We had some great presentations and tutorials, including me banging on about functional coverage, and Verilab’s Mark Litterick presenting some cool Assertion Based Verification techniques. We even managed to get some users to share their own tips and tricks, including our very own JL Gray.

I just got the stats for the fall 2007 meetings. 480 registered in total, 280 attended. Of the people surveyed (nearly everyone that attended the 5 meetings), 60% were using SystemVerilog today. Verification did pretty well out of that, with 67% of the share. Design got 10% and 23% said they used SystemVerilog for both design and verification. From a verification point of view another interesting stat was that 33% of the verification slice, were using the advanced testbench features of the language, and 32% were using SVA. It’s nice to see that more people are starting to use the HVL portion of the language for verification, not just writing assertions. I think this is due in no small to much better tool support and stability by all the vendors.

The growing attendance numbers of the SVUG meetings is a reflection of the interest and uptake of SystemVerilog by the design/verification community. I’m seeing an increase in our client projects using SystemVerilog Verification IP, and finding ways to hook SystemVerilog into their verification environments. Finally, it’s really beginning to feel like SystemVerilog is starting to make a bit of an impact.

Casting Strings to Enums in SystemVerilog

Sunday, October 21st, 2007 by JL Gray

Every once and awhile, I want to convert a string to an enumeration in SystemVerilog.  Casting from strings to enums is not supported in SystemVerilog, but luckily, it is possible to implement a function to do the appropriate conversion using built in methods designed for iterating over the enum values: 


Upcoming SVUG Events

Sunday, September 23rd, 2007 by JL Gray

svug_logoThose of you who are members of the SystemVerilog User Group (SVUG) may have received an email describing several upcoming events.  For those of you not on the SVUG mailing list, here is the info:

SVUG has a simple goal to advance the SystemVerilog language and accelerate the adoption of associated tools, methods, IP, and training. If you are a design or verification professional looking for a fun, informative way to keep on top of the SystemVerilog ecosystem, then you absolutely should register for a fall user group meeting at one of following locations:

USA Europe
Boston, MA
October 15th
Cafe Escadrille
Cambridge, UK
October 9th
Homerton College
Austin, TX
October 17th
Cool River Cafe
Munich, DE
October 11th
Sofitel Munich Bayerpost
San Jose
October 18th

These great locations will stimulate your SystemVerilog intellect with instructive tutorials and informative presentations, wonderful food & drink and best of all - the chance to mingle with your peers and the industries’ top SystemVerilog experts.

Click here to view each location’s agenda and schedule.

Verilab’s very own Jason Sprott and Mark Litterick will be presenting at a couple of the events.  Jason is presenting in Cambridge.  Mark is presenting in Munich.  If you’ve got a bit of spare time and are looking to learn more about SystemVerilog and meet up with other SV users, this is your chance! 

SystemVerilog Methodologies – It’s Getting Wild

Thursday, June 7th, 2007 by Jason Sprott

Every day this week at DAC I’ve been involved in at least one discussion on VMM versus AVM. It’s getting really competitive now. There’s all this talk of standards, Open Source, maturity, and compliance. On top of that, things just don’t stay still long enough to form an opinion that lasts more than five minutes.


Verilab Join Synopsys VMM Catalyst Program

Thursday, June 7th, 2007 by Jason Sprott

At DAC this week Synopsys announced the new VMM Catalyst Program, with over 50 founding members (including Verilab). Members of the VMM Catalyst Program get access to the Synopsys VCS Verification Library as well as the SystemVerilog source code for the VMM Standard Library.

Synopsys SystemVerilog Support

Wednesday, April 18th, 2007 by JL Gray

According to a helpful representative at the Synopsys booth this afternoon, VCS supports 99% of the SystemVerilog Testbench features. Which 99%? I’m aware it doesn’t support parameterized classes or the shuffle() method for arrays. I’m sure there must be more features as well. Also, a heads up. While browsing through the VCS documentation recently I discovered documentation on AOP extensions for SystemVerilog built into VCS. I haven’t tried it out yet to see if it works. However, as with Vera, the AOP support is nothing like the “when inheritance” found in Specman/e. When Inheritance allows fields, methods, and additions to methods to be added into an instance of a class only when a given field has been randomly set to a specified value.

Also useful to know? The 2006.06-12 release of VCS fixes several bugs in the graphical debugger (DVE) related to SystemVerilog.

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