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Archive for the ‘SystemVerilog’ Category

Silicon Valley SNUG: Sub-cycle Functional Timing Verification Using SystemVerilog Assertions

Tuesday, March 26th, 2013 by Paul Marriott

Verilab’s Anders Nordstrom will be presenting his paper “Sub-cycle Functional Timing Verification using SystemVerilog Assertions” at the Tuesday March 26th session at 10:30 am of SNUG Silicon Valley 2013.

This presentation shows a novel, more complete approach to functional verification of sub-cycle timing using SystemVerilog assertions in an OVM verification environment. This approach found many bugs which otherwise were missed in OVM-only simulations that didn’t include assertions.

This functional sub-cycle timing behaviour includes maintaining fixed delays and phase relationships between inputs and outputs and ensuring there are no glitches on clocks or delayed signals.

SystemVerilog assertions are evaluated on successive occurrences of an event or timing expression. This presents a challenge for sub-cycle timing verification, where there is no obvious reference clock suitable for triggering the assertions. Assertions sample their expressions in the preponed region of the simulation timestep, but the requirements called for sampling both before and after each triggering point. Examples of assertions showing how to overcome this and many other issues will be shown along with recommendations on how to write assertions for functional timing verification.

This paper is complementary to the paper presented by Paul Marriott at DVCon 2013 entitled Run-time Configuration of a Verification Environment - A Novel Use of the OVM/UVM Analysis Pattern. The sub-cycle timing relationships were dynamically varied during simulation and the assertions used were required to check for correctness as the actual relationships varied during the simulation.

UVM Phasing Survey

Tuesday, December 4th, 2012 by JL Gray

Verilab is currently conducting a survey to find out how SystemVerilog/UVM users are, well, using phasing and phase jumping. We would greatly appreciate your feedback! Click on the link below to take the survey.

UVM Runtime Phasing and Phase Jumping Survey

Verilab at DAC, SNUG Technical Committee Award

Tuesday, May 29th, 2012 by Paul Marriott

With the 49th DAC almost upon us, design and verification engineers will inevitably be thinking of the latest and greatest tools on offer from the EDA vendors. Despite complaints of ever increasing complexity being a problem, somehow the tools we’ve been using for the past several decades have been good enough to allow Moore’s Law to continue unabated, with 22nm technology being the latest production point on this exponential curve. Verilab will be there, as usual, to cover this important event and our VP and blogger-in-chief, JL Gray will be covering this over on Cool Verification.

As much as new shiny tools are interesting, sometimes it’s interesting to focus on some more mundane aspect of verification. Often verifiers are faced with what appears to be a simple problem, but which isn’t implemented in any vendor-neutral methodology. It’s always tempting to use tool-specific code, but fewer companies have the ability to restrict themselves to only one vendor over the lifetime of a product and its subsequent revisions. This is where methodologies such as the UVM are particularly useful. However, as much as they are touted as the solution to today’s verification problem, they often are missing some features which make a verifier’s job easier.

One such example is the ability to monitor value changes on arbitrary signals in the DUT without having to have a lot of hard-coded cross-module references. Such references make re-usability difficult, either when a block is reused in a top-level environment or in a completely different environment altogether. It would be nice if such references could be simply specified as strings and then advantage could be taken of the UVM’s configuration database to set and appropriate string for the use-case in question. However, such a facility is not part of the UVM right now.

Fortunately, Verilab’s Jonathan Bromley was motivated enough, when faced with this problem in a real project, to come up with a novel package that uses the SystemVerilog VPI/DPI to neatly provide a solution that works in the three major simulators that support the UVM. Jonathan  presented his paper on this at SNUG Munich on May 23rd and at SNUG UK on May 24th. His paper received the Technical Committee’s “Best Paper Award”.

SNUG 2009 Multi-Stream Scenario Paper Now Available

Saturday, April 18th, 2009 by JL Gray

Verilab’s award-winning paper entitled “Using the New Features in VMM 1.1 for Multi-Stream Scenarios” is now available for download from the Verilab website. Please let us know if you have any questions!

Litterick’s OCP-IP newsletter article uses Verilab’s OCP uVC VIP as an example

Wednesday, January 7th, 2009 by Jason Sprott

Mark Litterick’s OCP-IP December 2008 newsletter article demonstrates how two key aspects of OCP – profiles and transactions — were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems.

The article uses the Verilab OCP uVC as an example. This uVC is a mixed-language OCP compliant verification component that supports a major subset of Open Core Protocol Specification 2.2. The OCP uVC is implemented using SystemVerilog and e verification languages and complies with both the Open Verification Methodology (OVM) and e Reuse Methodology (eRM). The verification component can be used in SystemVerilog only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular eVC.

The OCP-IP article can be downloaded here

The full whitepaper can be downloaded here

DAC 2008 Presentations Now Posted

Wednesday, July 30th, 2008 by JL Gray

Just a quick FYI… both David Robinson and I have posted our DAC presentations on Verification Planning and SystemVerilog Interoperability on the Verilab website. Please check them out and let us know if you have any questions or comments!

SystemVerilog Gotcha: (when copying) a struct is not a class by another name

Sunday, January 20th, 2008 by Jason Sprott

SystemVerilog has two “similar” data types that allow variables to be grouped together in a handy package: the struct and the class. I’ve heard it often said, when explaining what a class (an object-oriented data type) is, that it is just like a C struct with functions. I used to have no problem with that, until, when reviewing and debugging testbench code, I started seeing some problems related to the way classes have to be treated differently to structs. One of the most common errors I’ve found is when data structures composed of classes are copied.

Consider the following: (more…)

SystemVerilog User Group 2007 Fall Meeting Stats

Wednesday, November 7th, 2007 by Jason Sprott

SVUG started in March 2007 and has had a total of 8 meetings so far. It’s been a great first year for all of us involved with SVUG. The meetings and forum have been met with real enthusiasm. We’ve had some interesting technical discussions with new and experienced developers using SystemVerilog on their projects. We had some great presentations and tutorials, including me banging on about functional coverage, and Verilab’s Mark Litterick presenting some cool Assertion Based Verification techniques. We even managed to get some users to share their own tips and tricks, including our very own JL Gray.

I just got the stats for the fall 2007 meetings. 480 registered in total, 280 attended. Of the people surveyed (nearly everyone that attended the 5 meetings), 60% were using SystemVerilog today. Verification did pretty well out of that, with 67% of the share. Design got 10% and 23% said they used SystemVerilog for both design and verification. From a verification point of view another interesting stat was that 33% of the verification slice, were using the advanced testbench features of the language, and 32% were using SVA. It’s nice to see that more people are starting to use the HVL portion of the language for verification, not just writing assertions. I think this is due in no small to much better tool support and stability by all the vendors.

The growing attendance numbers of the SVUG meetings is a reflection of the interest and uptake of SystemVerilog by the design/verification community. I’m seeing an increase in our client projects using SystemVerilog Verification IP, and finding ways to hook SystemVerilog into their verification environments. Finally, it’s really beginning to feel like SystemVerilog is starting to make a bit of an impact.

Casting Strings to Enums in SystemVerilog

Sunday, October 21st, 2007 by JL Gray

Every once and awhile, I want to convert a string to an enumeration in SystemVerilog.  Casting from strings to enums is not supported in SystemVerilog, but luckily, it is possible to implement a function to do the appropriate conversion using built in methods designed for iterating over the enum values: 


Upcoming SVUG Events

Sunday, September 23rd, 2007 by JL Gray

svug_logoThose of you who are members of the SystemVerilog User Group (SVUG) may have received an email describing several upcoming events.  For those of you not on the SVUG mailing list, here is the info:

SVUG has a simple goal to advance the SystemVerilog language and accelerate the adoption of associated tools, methods, IP, and training. If you are a design or verification professional looking for a fun, informative way to keep on top of the SystemVerilog ecosystem, then you absolutely should register for a fall user group meeting at one of following locations:

USA Europe
Boston, MA
October 15th
Cafe Escadrille
Cambridge, UK
October 9th
Homerton College
Austin, TX
October 17th
Cool River Cafe
Munich, DE
October 11th
Sofitel Munich Bayerpost
San Jose
October 18th

These great locations will stimulate your SystemVerilog intellect with instructive tutorials and informative presentations, wonderful food & drink and best of all - the chance to mingle with your peers and the industries’ top SystemVerilog experts.

Click here to view each location’s agenda and schedule.

Verilab’s very own Jason Sprott and Mark Litterick will be presenting at a couple of the events.  Jason is presenting in Cambridge.  Mark is presenting in Munich.  If you’ve got a bit of spare time and are looking to learn more about SystemVerilog and meet up with other SV users, this is your chance! 

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