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DVCon EU & SNUG Austin 2018

Thursday, October 18th, 2018 by Alex Melikian

This month, Verilab consultants will be participating in, and presenting at two conferences on two continents.

On October 23rd, award-winning authors Jeffrey Montesano and Jeff Vance will present “Use the Sequence, Luke! Guidelines to Reach the Full Potential of UVM Sequences” at SNUG Austin 2018. This presentation covers guidelines for optimizing control, effectiveness, debugging and reuse of UVM sequences, based on extensive project experience of complex designs. More details here.

Furthermore, multi-award winning consultant Mark Litterick will run a “UVM Audit: Assessing UVM Testbenches” tutorial at DVCon Europe on October 24th. This tutorial presents strategies and guidelines for auditing UVM code to identify and address reuse, flexibility and effectiveness of a testbench. More details here.

As always, we look forward to meeting people and sharing ideas in the verification community. For a look at our past conference papers and presentation, follow the link here:
http://www.verilab.com/resources/papers-and-presentations/

IEEE Std.1800-2017 for SystemVerilog: What Changed?

Sunday, February 25th, 2018 by Paul Marriott

Thoughts on the updated standard, by Principal Consultant Jonathan Bromley

A new revision

On Thursday 22nd February 2018, the latest revision of the IEEE standard for the SystemVerilog language was published as IEEE Std.1800-2017 (yeah, I know that’s so last year, but you can’t fight the way these things work). Thanks to the generosity of Accellera www.accellera.com and its member companies, the full standard document – the language reference manual, or LRM –is available free of charge through the GetIEEE program at http://ieeexplore.ieee.org/document/8299595/. You’ll need an IEEE login to download it, but you can get one for free by following the links on that page.

How can I figure out what’s different?

Within hours of publication, colleagues were asking me the reasonable question “what’s new?” In principle you shouldn’t need to ask. The SystemVerilog standards development process is highly transparent. Anyone can read the LRM, and anyone can follow the progress of committee discussion by watching the Mantis bug tracker https://accellera.mantishub.io. In practice, though, I’ve saved you a load of trouble by slugging my way through all the issues that made the cut into 1800-2017 and creating the summary of changes that you’ll find later in this post.

How did we get to where we are today?

SystemVerilog first saw public light of day as an Accellera standard way back in 2003. Vendors rallied behind it, users were enthusiastic, and Accellera wisely passed the standard into the care of the IEEE. The first gold-plated, fully-official IEEE SystemVerilog standard appeared in 2005. There were significant revisions in 2009 and 2012, each adding important new features and functionality to an already large and rich language. Spurred on by the development and rapid adoption of the Universal Verification Methodology, commercial implementations of SystemVerilog became increasingly mature so that everyone could use the language with confidence (and, of course, with caution to avoid a few things that didn’t enjoy perfect support from all the available tools).

So, what happened since 1800-2012?

How can you have a SystemVerilog revision with no new features? Everyone has pet features that they would like to see in SystemVerilog. A ton of them got added in the 2009 and 2012 revisions – here are a few that I use routinely:

For 2017, though, the remit was clear: no new features. Boy, did we have to bite our tongues in the committee discussions (and no, I’m not allowed to tell you anything about what happened in them). The focus? Corrections, clarifications and improvements of LRM text – great news for anyone who tries to write code that will work reliably on any commercially available tools.

C’mon, spill the beans: How many changes?

As far as I can tell, 108 distinct Mantis issues made the cut and were fully resolved in time for incorporation into 1800-2017 by the editor. This is a good moment for a hat-tip to the tireless Shalom Bresticker, who served as LRM editor for this revision. His encyclopaedic knowledge of SystemVerilog, razor-sharp attention to detail, and diligent curation of the Mantis issue tracker made a huge contribution to the project’s success.

Just the words

Of those 108 issues, 69 were purely editorial or wordsmithing changes, improving LRM text or internal consistency without any technical controversy.

Whoops, we missed a few things in the VPI

There were three changes to the VPI header file vpi_user.h to fix some minor oversights.

Clarifications to provide a solid base for vendors and users

30 issues were minor clarifications that are probably only of interest to the most dedicated and obsessive LRM wonk. Stuff like typesetting of the BNF syntax rules in Annex A, a tightening-up of the strict definition of property vacuity, and improvements or corrections of a few code examples. However, some of these clarifications are worth a closer look. Take a peek at these Mantis items to learn more:

But that was just the small stuff. What about the big-ticket items?

Of the 108 changes, just five by my reckoning were significant changes of definition. None of these are new language features. They’re just cleanups of areas of the standard that were too sloppy or just plain wrong. Some of those problem areas had led to incompatible divergence between different vendors’ implementations. Some were wrinkles in the language that were effectively un-implementable or too error-prone, and needed to be ironed out. Here they are, one by one:

  1. Issue 343: modport declarations in generate blocks

    In the early days of SystemVerilog, a few brave engineers tried to use interfaces to Do Interesting Things in RTL design. Yes, you guessed it – I’m guilty, along with a few others. One of the things we thought was cool: representing a set of connections to an interface by using a modport, which could then be instantiated more than once in the interface. So you define a modport to represent – let’s say – a slave device’s connection to a bus fabric. And then you instantiate an array of those modports, so that an array of slaves can connect to them.

    Oh my, were we wrong. Brave, but wrong.

    A modport isn’t a thing you can instantiate.

    If you ever thought that using modports like this was a good idea, then read the Mantis ticket and weep. It isn’t. And you’re not allowed to do it any more. Modports are no longer allowed to appear inside a generate block.

    There are other, better ways to get the same result that will make good material for a future blog post.

  2. Issue 2488: calling virtual methods from a class’s constructor

    Wise programmers know that it’s a bad idea to call a virtual method of any class from the class’s constructor. Different object-oriented languages deal with this situation in different ways, and it’s tricky. Unfortunately it was never properly defined in SystemVerilog – until now. Thanks to that lack of definition, different simulators behaved in different, incompatible ways. The required behaviour is now clearly defined, although it may take a while before tools converge on that behaviour.

    Wise programmers will continue to avoid calling virtual methods from the constructor. The effects are gnarly and far from intuitive.

  3. Issue 4939 and 5540: randomization of enums

    These two corrections deal with some interesting issues about randomization of enum variables. The enum literals define a set of possible values. Should that be treated as a constraint on the enum? What happens if the enum is a member of a packed struct? Once again these are questions that weren’t properly answered, and simulators had begun to diverge. There’s now a clear definition of how it all works. Check your favourite simulator to see how it stacks up against the new definition.

  4. Issue 5183: syntax of pragma expressions

    This fixes some problems in the definition of “protected envelopes”, SystemVerilog’s mechanism for delivering encrypted source code. It’s likely to be of interest mainly to IP vendors.

  5. Issue 5217: operator overloading removed

    Yes, you read it correctly. The operator overloading feature, which has never been implemented by any tool that I know about, has been removed from the LRM. The feature was never properly defined, and there were too many difficulties with the definition for it to be retained.

    This isn’t the first time a feature has been completely deleted from SystemVerilog, but it’s probably the most significant.

So Long, And Thanks For All The Syntax

Thanks for reading this roundup of the changes in SystemVerilog for the 2017 revision. That revision also marks the end of my own involvement with SystemVerilog standardization, as I stand down from the standardization process.

I’ve been honoured (with a U, me being a Brit – apologies to anyone west of Iceland who doesn’t like the spelling) to serve on SystemVerilog standards working groups for nearly 14 years. I don’t use the word “honour” lightly. It’s been a huge privilege to work alongside the exceptionally smart and dedicated people who, supported by their employers, have given time and expertise to make SystemVerilog better for the whole EDA community – an enormous effort in which I’ve made a few tiny contributions. It’s been an amazing journey, engaging with the development of a programming language that is almost synonymous with digital hardware design and verification. It’s introduced me to an astonishing group of talented, enthusiastic, generous-spirited experts from vendor and user companies. Many of those people – you know who you are – have taught me a huge amount, and I’m deeply grateful.

Any errors in this summary are mine alone; if you find any, please get in touch at jonathan.bromley@verilab.com and I’ll be happy to correct them and acknowledge your contribution.

25 February 2018

Verilab at DVCon 2018

Thursday, February 22nd, 2018 by Paul Marriott

Come and join Verilab at DVCon 2018 in San Jose, CA from February 26th to March 1st.

Verilab’s Vice President Vanessa Cooper has once again served as the Panel Chair in order to present two interesting and pertinent discussion topics on Wednesday Feb 28th. The first one, titled “Help! System Coverage is a Big Data Problem” will have panelists explore how Portable Stimulus, formal verification, and emulation can be used to help provide confidence in closing system coverage. The second one, titled “The Right Tool(s) for the Toughest Verification Tasks” will cover and debate which available verification tools are best suited for particular tasks, and why some tools tend to dominate over others.

In addition to the panels, Principal Consultant Jonathan Bromley will also conduct a “Formal Verification in the Real World” workshop on Thursday March 1st. Built on the foundation level tutorial “Formal Verification – Too Good to Miss” presented at DVCon Europe 2017, this workshop will provide a quick ramp-up on the next steps to expand Formal Verification practices on your projects. Furthermore demystifying some of the more advanced techniques that are easy enough to use but often tricky to learn.

Last but not least, Senior Consultant Jeff Vance will present “My Testbench Used to Break! Now it Bends” on Tuesday 27th at 15:00 in the Carmel Room. The presentation will detail a solution that allows your UVM testbench architecture to adapt to different design configurations without impacting interface connections. The result is a reusable testbench that can be migrated to future projects with minimal changes.

As always, we look forward to meeting people and sharing ideas in the verification industry. For our past conference papers and presentation, please consult the Papers and Presentations section of our website.

SNUG Austin 2017 – UVM Harness Presentation

Monday, October 16th, 2017 by Alex Melikian

Verilab will lead a strong presence at SNUG Austin 2017, with consultants Jeff Montesano and Jeff Vance presenting “Verification Prowess with the UVM Harness” on Thursday, October 19th.

Based on their paper, the presentation will explore powerful and highly applicable techniques in the domain of testbench to DUT connection, blazing a path towards achieving verification prowess in projects of all levels. Details will be provided showing how any testbench can use the harness to manage connections more easily while allowing you to manipulate the roles of agents without impact to interface connections. Furthermore, demonstrations will be given on how the presented solution allows UVM testbench developers to apply powerful verification strategies that would not be possible with traditional connections.

More details of this presentation, along with other conference details, can be found here:

https://event.synopsys.com/ehome/277997/Agenda/

Verilab looks forward to taking the opportunity and engage with the verification community at conferences like SNUG Austin. All our past published conference papers and presentations can be found here:

http://www.verilab.com/resources/papers-and-presentations/

See you at SNUG Austin 2017!

DVCon Europe 2017 – Formal Verification Tutorial & UVM Multi-Language Presentation

Thursday, October 12th, 2017 by Alex Melikian

Verilab is proud to participate at DVCon Europe 2017 with a tutorial and presentation given by our own Jonathan Bromley and Thorsten Dworzak.

Firstly on Monday October 16th, senior consultant Jonathan Bromley will be giving the “Formal Verification in the Real World” tutorial. Based on our well received foundation level tutorial from the 2016 conference, this year’s session will cover some of the more advanced techniques and workflow patterns on one of the most talked about areas of verification. More details here:

https://dvcon-europe.org/content/event-details?id=234-1-T

Whereas on Tuesday October 17th, principal engineer Thorsten Dworzak will co-present “UVM Multi-Language Library: Hands-On” with Angel Hidalga of Infineon Technologies. The presentation covers their work of developing a simulator independent library extension of the UVM, promising easy integration of different high-level verification languages. More details here:

https://dvcon-europe.org/content/event-details?id=234-5

Verilab looks forward to hearing from the verification community and their thoughts about these or any other verification topics. As always, all our past published conference papers and presentations can be found here:

http://www.verilab.com/resources/papers-and-presentations/

See you there!

Verilab at CDNLive Munich 2017 May 16

Monday, May 15th, 2017 by Paul Marriott

We’re proud to announce Verilab consultant Thorsten Dworzak will be presenting at CDNLive Munich 2017 this Tuesday May 16th.

Thorsten will be presenting his paper, entitled “UVM-ML: Message from the Trenches” in the FV 15 track at 14:30 in the Chiemsee room of the INFINITY Hotel & Conference Resort.

Abstract

The UVM multi-language package version 1.2 and its integration into Cadence IES promise easy integration of different high-level verification languages. We applied it together with previously existing techniques to attach a SystemC model to different UVM-SV testbenches. The interface between the two worlds has been implemented using TLM2, DPI-C, and FMI. Over the course of this project we faced some obstacles and stumbling blocks across different aspects. By sharing our experience and some resulting guidelines, we hope to provide others with a smoother experience.

For the verification of an ARM CPU IP we developed a SystemC model. The model serves two different verification focuses. First, it is used as reference model for the DUT in a fully-featured UVM testbench. The testbench provides stimuli generation, scoreboarding, and coverage. Stimuli generation and scoreboarding are using their own C-model instance with a slightly different feature set. Both model instances receive CPU instructions from the testbench.

Second, it is used as stand-alone instruction-set simulator (ISS), embedded in a UVM testbench that mainly provides shared memory and allows running a set of self-checking assembler tests. This testbench can use either the model or the DUT as a drop-in component. The C-model operates in master mode, i.e. it fetches CPU instructions from the shared memory.

Third, the C-model is going to be used in a software simulator, which determines the performance requirements.

In this publication we will mainly focus on the reference model (scoreboard) use-case.

We look forward to seeing you there.

Verilab at SNUG Ottawa 2017 April 21

Thursday, April 13th, 2017 by Paul Marriott

We’re proud to announce Verilab consultant Alex Melikian will be presenting at SNUG Ottawa 2017 next Friday April 21st.

Alex will present his paper, jointly authored with Paul Marriott, “Perplexing Parameter Permutation Problems? Immunize Your Testbench” at 3:30 in the Verification-I track.

For more information on times and events consult the schedule, or download the SNUG Ottawa mobile app.

To download any of our previous papers and presentation, check out our “Papers and Presentations” page.

We look forward to seeing you there.

Tribute to Scott Roland

Friday, April 7th, 2017 by Paul Marriott

Scott Roland

It is with great sadness that we announce the passing of our friend and colleague Scott Roland. He died on April 2nd, 2017, surrounded by his family and friends, following complications in battling a recent illness.

Born in the United States, and a graduate of Brown University Computer Science, Scott was an accomplished chip design and verification engineer. By 2007, his work had already taken him to Switzerland from where he then moved to Germany to join the Verilab Munich team in January 2008. As a consultant, Scott was a key contributor to a range of important chip projects across Europe, his work taking him to clients not only in Germany, but also Ireland, Sweden, Scotland, and Austria. A specialist in the complex computing infrastructures that underpin modern chip design efforts, Scott made significant improvements in the use of version control and build automation systems in all of the projects on which he worked, saving his teams many weeks and months of valuable design cycle time.

In addition, Scott brought the ingenuity of the “born engineer” to all aspects of his work be it in rooting out deep design bugs, fixing bugs in the design and verification tools themselves, or even as far as helping decide on the correct font for editing code, a decision of such importance that wars have been started for less. Perhaps the best example of Scott’s combination of attention to detail and MacGyver-like inventiveness was in his design of a standing desk. Clearly having been influenced by German frugality, Scott avoided the expense of buying a ready-made system and instead acquired some cinder blocks and used those to raise his existing desk a few feet.

A Swabian thriftiness was not the only aspect of his adopted home’s culture that Scott and his wife Julie acquired. Keen observers of, and participants in, the cultures of all the countries in which they spent time, Scott and Julie took the German posting as an opportunity to enthusiastically embrace all things Bavarian. He wore his lederhosen with pride —especially at Oktoberfest—with Julie completing the picture resplendent in traditional dirndl. Then shortly after moving to the Verilab Edinburgh office in November 2012, he dived straight into the Scottish scene by attending a Burns Night supper at a colleague’s house. Perhaps it was a little bit too much culture too quickly though, because he was heard to comment, amid the sound of bagpipes, that, “Mercifully Yammer [Verilab's internet messaging tool of choice] doesn’t do audio!

Scott Roland - August 2016

Scott Roland - August 2016

Scott is survived by Julie, an accomplished artist living in Edinburgh. Julie took this picture of him, commenting, “This photo is one of my favorites. It was taken back in August. Scott was in the middle of receiving his second round of chemo at the hospital in Edinburgh. He felt so well that we passed on hospital lunch and went out to eat at a local pub instead.’

DVCon 2017: “SV Jinxed Half My Career” Panel Preview

Tuesday, February 7th, 2017 by Alex Melikian

Verilab is proud to have senior consultant Jonathan Bromley host the “SystemVerilog Jinxed Half My Career” panel at DVCon 2017, on Wednesday March 1st. Jonathan continues to serve on the SystemVerilog IEEE committee and is the author of numerous papers, including the recently published “Slicing Through the UVM’s Red Tape”. We took a moment with Jonathan to preview what this panel will cover and what those planning or thinking of attending should expect.


The title is “SystemVerilog Jinxed Half My Career : Where do we go from here”, which signals this panel will focus on areas of improvement. What are those areas of frustration in SystemVerilog you feel need improvement?

It would be easy to give a “where do I start?” response, and it’s not difficult to come up with a laundry list of desirable SystemVerilog improvements and nit-picky complaints. But this is DVCon, and our very knowledgeable and sophisticated audience deserves better. We have five extraordinarily experienced panelists and I hope we can venture beyond details of the languages and tools we have today, and think creatively about what we can and should hope for in the mid-term future. Many languages have been used successfully to create advanced testbenches - ‘e’, C++, Python, Vlang - but there’s no question that SystemVerilog remains dominant. Why is that? What sort of code will verification engineers be writing in five, ten years’ time?
(more…)

DVCon Europe 2016: Slicing Through the UVM’s Red Tape - A Frustrated User’s Survival Guide

Tuesday, October 18th, 2016 by Paul Marriott

Jonathan Bromley will be presenting a paper on Thursday 20th, in session 1 (3:15-4:30PM), examining some of the challenges and frustrations for novice and intermediate-level users of the UVM on real projects.

This paper looks at typical examples of such challenges, and offers solutions that respect fundamental aims of the UVM: consistency, reusability, and expressive power.

If you’ve struggled with the integration of directed tests, external models into the sequences mechanism, reconciling the abstract and the untimed nature of sequences with the need for precise control over stimulus timing, proper use of the configuration database, or working with a parameterized device-under-test, this presentation might be for you.

A full description of the tutorial is detailed in the DVCon Europe 2016 conference program

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