We’re hiring in Austin. Check out our LinkedIn job advert for details.

Come join us at DVCon 2012 in San Jose, CA. Several of us from Verilab will be involved in the following activities:

• Monday, February 27 - UVM: Ready, Set, Deploy. Vanessa Cooper presenting.
• Tuesday, February 28 - Industry Leaders Panel: The Resurgence of Chip Design. Moderator: JL Gray
• Tuesday, February 28 - A 30-Minute Project Makeover Using Continuous Integration. JL Gray and Gordon McGregor

Verilab will also be sponsoring this year’s best paper award. We look forward to seeing you there!

Rumor has it we’ve been staffing a team in Canada with engineers in Ottawa and Montreal. If you’re interested in joining go ahead and submit an application today!

Verilab’s award-winning paper entitled “Using the New Features in VMM 1.1 for Multi-Stream Scenarios” is now available for download from the Verilab website. Please let us know if you have any questions!

Verilab have added their OCP uVC verification component to the OCP-IP Library.

The Verilab OCP uVC is a mixed language verification component for the Open Core Protocol (OCP) implemented using SystemVerilog and e verification languages. It can be used as an Open Verification Methodology (OVM) Verification Component (OVC) in SystemVerilog-only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular e Verification Component (eVC).

The datasheet for the OCP uVC can be downloaded here

Mark Litterick’s “Architecting the OCP uVC verification component” article written about in a previous blog has also been picked up by EDA Designline

Mark Litterick’s OCP-IP December 2008 newsletter article demonstrates how two key aspects of OCP – profiles and transactions — were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems.

The article uses the Verilab OCP uVC as an example. This uVC is a mixed-language OCP compliant verification component that supports a major subset of Open Core Protocol Specification 2.2. The OCP uVC is implemented using SystemVerilog and e verification languages and complies with both the Open Verification Methodology (OVM) and e Reuse Methodology (eRM). The verification component can be used in SystemVerilog only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular eVC.

The OCP-IP article can be downloaded here

The full whitepaper can be downloaded here

Just a quick FYI… both David Robinson and I have posted our DAC presentations on Verification Planning and SystemVerilog Interoperability on the Verilab website. Please check them out and let us know if you have any questions or comments!

There was a recent surge of discussions about asynchronous clock domain crossings and metastability handling in Verilab email: Two people asked Mark Litterick essentially the same question just hours apart, and then a day later Jason Sprott noticed a Mentor CDC Verification paper that referenced Mark’s “Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter using SystemVerilog Assertions,” paper (Best Paper at DVCon 2006).

One particular statement in the Mentor paper caught my eye: "this model can still generate false errors: the waveforms show that input sequence A, B, C, D, E, F can result in output sequence A, B, E, E, E, where two consecutive inputs, C and D, are skipped". And this statement bothered me: I had spent a long time figuring out Mark’s model some while back, and while it was not at all intuitive to me, I did convince myself that it could never generate a simulated output sequence that was impossible in real hardware. So if the Mentor paper was correct, then I had missed something about Mark’s model, and I’ll be honest, I didn’t relish going back and studying it again.

Obviously I was just going to have to find a mistake in the Mentor paper instead. And to my considerable relief, I did. In fact, I found two:

1. The schematic (Fig 8, p.9) of Mark’s synchronizer model is missing a small but important feature.
2. The waveform (Fig 9, p.9) of data signal values input to the model is a somewhat misleading representation of an async input.

(more…)

SystemVerilog has two “similar” data types that allow variables to be grouped together in a handy package: the struct and the class. I’ve heard it often said, when explaining what a class (an object-oriented data type) is, that it is just like a C struct with functions. I used to have no problem with that, until, when reviewing and debugging testbench code, I started seeing some problems related to the way classes have to be treated differently to structs. One of the most common errors I’ve found is when data structures composed of classes are copied.

Consider the following: (more…)