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Archive for the ‘News’ Category

Verilab at CDNLive Munich 2017 May 16

Monday, May 15th, 2017 by Paul Marriott

We’re proud to announce Verilab consultant Thorsten Dworzak will be presenting at CDNLive Munich 2017 this Tuesday May 16th.

Thorsten will be presenting his paper, entitled “UVM-ML: Message from the Trenches” in the FV 15 track at 14:30 in the Chiemsee room of the INFINITY Hotel & Conference Resort.

Abstract

The UVM multi-language package version 1.2 and its integration into Cadence IES promise easy integration of different high-level verification languages. We applied it together with previously existing techniques to attach a SystemC model to different UVM-SV testbenches. The interface between the two worlds has been implemented using TLM2, DPI-C, and FMI. Over the course of this project we faced some obstacles and stumbling blocks across different aspects. By sharing our experience and some resulting guidelines, we hope to provide others with a smoother experience.

For the verification of an ARM CPU IP we developed a SystemC model. The model serves two different verification focuses. First, it is used as reference model for the DUT in a fully-featured UVM testbench. The testbench provides stimuli generation, scoreboarding, and coverage. Stimuli generation and scoreboarding are using their own C-model instance with a slightly different feature set. Both model instances receive CPU instructions from the testbench.

Second, it is used as stand-alone instruction-set simulator (ISS), embedded in a UVM testbench that mainly provides shared memory and allows running a set of self-checking assembler tests. This testbench can use either the model or the DUT as a drop-in component. The C-model operates in master mode, i.e. it fetches CPU instructions from the shared memory.

Third, the C-model is going to be used in a software simulator, which determines the performance requirements.

In this publication we will mainly focus on the reference model (scoreboard) use-case.

We look forward to seeing you there.

Verilab at SNUG Ottawa 2017 April 21

Thursday, April 13th, 2017 by Paul Marriott

We’re proud to announce Verilab consultant Alex Melikian will be presenting at SNUG Ottawa 2017 next Friday April 21st.

Alex will present his paper, jointly authored with Paul Marriott, “Perplexing Parameter Permutation Problems? Immunize Your Testbench” at 3:30 in the Verification-I track.

For more information on times and events consult the schedule, or download the SNUG Ottawa mobile app.

To download any of our previous papers and presentation, check out our “Papers and Presentations” page.

We look forward to seeing you there.

Tribute to Scott Roland

Friday, April 7th, 2017 by Paul Marriott

Scott Roland

It is with great sadness that we announce the passing of our friend and colleague Scott Roland. He died on April 2nd, 2017, surrounded by his family and friends, following complications in battling a recent illness.

Born in the United States, and a graduate of Brown University Computer Science, Scott was an accomplished chip design and verification engineer. By 2007, his work had already taken him to Switzerland from where he then moved to Germany to join the Verilab Munich team in January 2008. As a consultant, Scott was a key contributor to a range of important chip projects across Europe, his work taking him to clients not only in Germany, but also Ireland, Sweden, Scotland, and Austria. A specialist in the complex computing infrastructures that underpin modern chip design efforts, Scott made significant improvements in the use of version control and build automation systems in all of the projects on which he worked, saving his teams many weeks and months of valuable design cycle time.

In addition, Scott brought the ingenuity of the “born engineer” to all aspects of his work be it in rooting out deep design bugs, fixing bugs in the design and verification tools themselves, or even as far as helping decide on the correct font for editing code, a decision of such importance that wars have been started for less. Perhaps the best example of Scott’s combination of attention to detail and MacGyver-like inventiveness was in his design of a standing desk. Clearly having been influenced by German frugality, Scott avoided the expense of buying a ready-made system and instead acquired some cinder blocks and used those to raise his existing desk a few feet.

A Swabian thriftiness was not the only aspect of his adopted home’s culture that Scott and his wife Julie acquired. Keen observers of, and participants in, the cultures of all the countries in which they spent time, Scott and Julie took the German posting as an opportunity to enthusiastically embrace all things Bavarian. He wore his lederhosen with pride —especially at Oktoberfest—with Julie completing the picture resplendent in traditional dirndl. Then shortly after moving to the Verilab Edinburgh office in November 2012, he dived straight into the Scottish scene by attending a Burns Night supper at a colleague’s house. Perhaps it was a little bit too much culture too quickly though, because he was heard to comment, amid the sound of bagpipes, that, “Mercifully Yammer [Verilab's internet messaging tool of choice] doesn’t do audio!

Scott Roland - August 2016

Scott Roland - August 2016

Scott is survived by Julie, an accomplished artist living in Edinburgh. Julie took this picture of him, commenting, “This photo is one of my favorites. It was taken back in August. Scott was in the middle of receiving his second round of chemo at the hospital in Edinburgh. He felt so well that we passed on hospital lunch and went out to eat at a local pub instead.’

DVCon 2017: “SV Jinxed Half My Career” Panel Preview

Tuesday, February 7th, 2017 by Alex Melikian

Verilab is proud to have senior consultant Jonathan Bromley host the “SystemVerilog Jinxed Half My Career” panel at DVCon 2017, on Wednesday March 1st. Jonathan continues to serve on the SystemVerilog IEEE committee and is the author of numerous papers, including the recently published “Slicing Through the UVM’s Red Tape”. We took a moment with Jonathan to preview what this panel will cover and what those planning or thinking of attending should expect.


The title is “SystemVerilog Jinxed Half My Career : Where do we go from here”, which signals this panel will focus on areas of improvement. What are those areas of frustration in SystemVerilog you feel need improvement?

It would be easy to give a “where do I start?” response, and it’s not difficult to come up with a laundry list of desirable SystemVerilog improvements and nit-picky complaints. But this is DVCon, and our very knowledgeable and sophisticated audience deserves better. We have five extraordinarily experienced panelists and I hope we can venture beyond details of the languages and tools we have today, and think creatively about what we can and should hope for in the mid-term future. Many languages have been used successfully to create advanced testbenches - ‘e’, C++, Python, Vlang - but there’s no question that SystemVerilog remains dominant. Why is that? What sort of code will verification engineers be writing in five, ten years’ time?
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DVCon Europe 2016: Slicing Through the UVM’s Red Tape - A Frustrated User’s Survival Guide

Tuesday, October 18th, 2016 by Paul Marriott

Jonathan Bromley will be presenting a paper on Thursday 20th, in session 1 (3:15-4:30PM), examining some of the challenges and frustrations for novice and intermediate-level users of the UVM on real projects.

This paper looks at typical examples of such challenges, and offers solutions that respect fundamental aims of the UVM: consistency, reusability, and expressive power.

If you’ve struggled with the integration of directed tests, external models into the sequences mechanism, reconciling the abstract and the untimed nature of sequences with the need for precise control over stimulus timing, proper use of the configuration database, or working with a parameterized device-under-test, this presentation might be for you.

A full description of the tutorial is detailed in the DVCon Europe 2016 conference program

DVCon Europe 2016: Formal Verification - Too Good To Miss

Monday, October 17th, 2016 by Paul Marriott

Jonathan Bromley and Jason Sprott will be delivering a tutorial on Wednesday 19th October 10:00-11:30AM at DVCon Europe 2016 in Munich.

We find that getting started on formal verification can be a challenge. It’s different to traditional simulation, with some unfamiliar concepts. However, for the right kind of problem, it’s just too good to miss out on due to the lack of experience. This tutorial aims to address that initial lack of confidence and basic knowledge, helping engineers to get started on real project work using formal verification. We’ll be using a small case study to take attendees through the lifecycle of a formal verification project for a block-level RTL design.

A full description of the tutorial is detailed in the DVCon Europe 2016 conference program

Verilab Presentations From SNUG Austin

Thursday, October 13th, 2016 by Paul Marriott

Jeff Montesano and Jeff Vance presented their paper entitled “Configuring a Date with a Model – A Guide to Configuration Objects and Register Models” at SNUG Austin this past September 2016.

The full paper and presentation slide can be downloaded from our resources section: snug2016model.

Jonathan Bromley, Mark Litterick, and Vanessa Cooper’s paper entitled “Effective SystemVerilog Functional Coverage: design and coding recommendations” can also be downloaded from our resources section: snug2016cover. Unfortunately, Vanessa was unable to present this due to sickness, though this paper did win the Technical Committee Honourable Mention Award at SNUG2016UK.

Thanks to all who attended!

All of our papers and presentations can be downloaded from our resources page’s papers-and-presentations section.

Verilab at SNUG Austin 2016

Monday, September 26th, 2016 by Alex Melikian

We’re proud to announce Verilab consultants Jeff Montesano, Jeff Vance and Vanessa Cooper will be presenting at SNUG Austin 2016 this Thursday September 29th.

Jeff Montesano and Jeff Vance will present “Configuring a Date with a Model – A Guide to Configuration Objects and Register Models” in the morning session. In addition, as conference technical chair, J. Montesano will have the pleasure to give a short address and introduce the morning keynote speakers.

Vanessa Cooper will present “Effective SystemVerilog Functional Coverage: Design and Coding Recommendations” in the afternoon session.

For more information on times and events consult the schedule, or download the “SNUG Austin” mobile app.

We look forward to seeing you there and hear what you have to say about verification.

“Formal Verification - Getting Started with Confidence” Webinar

Thursday, June 9th, 2016 by Alex Melikian

Here at Verilab, we’re seeing an increase in formal verification being used on client projects. The tools have come a long way, especially with formal “Apps” that focus on some specific activities, increasing automation for formal tasks.

Today’s formal tools are a serious alternative to simulation for many functional verification tasks. A strong understanding of the terminology, techniques and general tool capabilities is key for a successful adoption. Although the formal tools look different to one another and have different strengths and weaknesses, the underlying techniques are the same. The domain terminology used is consistent and there are standard input languages. Most of what you’ll need to learn applies to tools across the board.

Interested in dipping a toe in the water?

We’ve partnered with Doulos to deliver a FREE webinar “Formal Verification - Getting Started with Confidence”, an introductory session highlighting some key concepts. No experience with formal verification is required.

The webinar will be presented on June 17th, 2016. For more details and registration click here:
Formal Verification - Getting Started with Confidence


DVCon 2016 Best Paper / Poster Awards

Thursday, March 3rd, 2016 by Paul Marriott

Everyone at Verilab would like to congratulate the winners of the 2016 Best Paper and Poster awards which we were proud to sponsor.

BEST PAPER
1st Place

8.2: Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012
Speaker: Eldon G. Nelson - Intel Corp.

2nd Place

5.1: SystemVerilog Interface Classes - More Useful Than You Thought
Speaker: Stan Sokorac - ARM, Inc.

3rd Place

9.3: Functional Coverage Collection for Analog Circuits – Enabling Seamless Collaboration Between Design and Verification
Speaker:Zhipeng Ye - Texas Instruments, Inc.
Authors:Zhipeng Ye - Texas Instruments, Inc.
Honghuang Lin - Texas Instruments, Inc.
Asad Khan - Texas Instruments, Inc

BEST POSTER
1st Place

4P.32 Marrying Simulation and Formal Made Easier!
Speaker:Lun Li - Samsung Austin R&D Center
Authors:Lun Li - Samsung Austin R&D Center
Durga Rangarajan - Samsung Austin R&D Center
Christopher Starr - Samsung Austin R&D Center
James Greene - Samsung Austin R&D Center
Nitin Mhaske - Synopsys, Inc.

2nd Place

4P.22 Improving the UVM Register Model: Adding Product Feature Based API for Easier Test Programming
Speaker:Krishnan Balakrishnan - Analog Devices, Inc.
Authors:Krishnan Balakrishnan - Analog Devices, Inc.
Courtney Fricano - Analog Devices, Inc.
Kaushal M. Modi - Analog Devices, Inc.

3rd Place

4P.14 How Do You Verify Your Verification Components
Speakers:Neil Johnson - XtremeEDA Corp.
Joshua W. Rensch - Superion Technology

Authors:Joshua W. Rensch - Superion Technology
Neil Johnson - XtremeEDA Corp.

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