Verilab will lead a strong presence at SNUG Austin 2017, with consultants Jeff Montesano and Jeff Vance presenting “Verification Prowess with the UVM Harness” on Thursday, October 19th.

Based on their paper, the presentation will explore powerful and highly applicable techniques in the domain of testbench to DUT connection, blazing a path towards achieving verification prowess in projects of all levels. Details will be provided showing how any testbench can use the harness to manage connections more easily while allowing you to manipulate the roles of agents without impact to interface connections. Furthermore, demonstrations will be given on how the presented solution allows UVM testbench developers to apply powerful verification strategies that would not be possible with traditional connections.

More details of this presentation, along with other conference details, can be found here:

https://event.synopsys.com/ehome/277997/Agenda/

Verilab looks forward to taking the opportunity and engage with the verification community at conferences like SNUG Austin. All our past published conference papers and presentations can be found here:

http://www.verilab.com/resources/papers-and-presentations/

See you at SNUG Austin 2017!

Verilab is proud to participate at DVCon Europe 2017 with a tutorial and presentation given by our own Jonathan Bromley and Thorsten Dworzak.

Firstly on Monday October 16^th, senior consultant Jonathan Bromley will be giving the “Formal Verification in the Real World” tutorial. Based on our well received foundation level tutorial from the 2016 conference, this year’s session will cover some of the more advanced techniques and workflow patterns on one of the most talked about areas of verification. More details here:

https://dvcon-europe.org/content/event-details?id=234-1-T

Whereas on Tuesday October 17^th, principal engineer Thorsten Dworzak will co-present “UVM Multi-Language Library: Hands-On” with Angel Hidalga of Infineon Technologies. The presentation covers their work of developing a simulator independent library extension of the UVM, promising easy integration of different high-level verification languages. More details here:

https://dvcon-europe.org/content/event-details?id=234-5

Verilab looks forward to hearing from the verification community and their thoughts about these or any other verification topics. As always, all our past published conference papers and presentations can be found here:

http://www.verilab.com/resources/papers-and-presentations/

See you there!

Verilab is proud to have senior consultant Jonathan Bromley host the “SystemVerilog Jinxed Half My Career” panel at DVCon 2017, on Wednesday March 1st. Jonathan continues to serve on the SystemVerilog IEEE committee and is the author of numerous papers, including the recently published “Slicing Through the UVM’s Red Tape”. We took a moment with Jonathan to preview what this panel will cover and what those planning or thinking of attending should expect.

The title is “SystemVerilog Jinxed Half My Career : Where do we go from here”, which signals this panel will focus on areas of improvement. What are those areas of frustration in SystemVerilog you feel need improvement?

It would be easy to give a “where do I start?” response, and it’s not difficult to come up with a laundry list of desirable SystemVerilog improvements and nit-picky complaints. But this is DVCon, and our very knowledgeable and sophisticated audience deserves better. We have five extraordinarily experienced panelists and I hope we can venture beyond details of the languages and tools we have today, and think creatively about what we can and should hope for in the mid-term future. Many languages have been used successfully to create advanced testbenches - ‘e’, C++, Python, Vlang - but there’s no question that SystemVerilog remains dominant. Why is that? What sort of code will verification engineers be writing in five, ten years’ time?
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We’re proud to announce Verilab consultants Jeff Montesano, Jeff Vance and Vanessa Cooper will be presenting at SNUG Austin 2016 this Thursday September 29^th.

Jeff Montesano and Jeff Vance will present “Configuring a Date with a Model – A Guide to Configuration Objects and Register Models” in the morning session. In addition, as conference technical chair, J. Montesano will have the pleasure to give a short address and introduce the morning keynote speakers.

Vanessa Cooper will present “Effective SystemVerilog Functional Coverage: Design and Coding Recommendations” in the afternoon session.

For more information on times and events consult the schedule, or download the “SNUG Austin” mobile app.

We look forward to seeing you there and hear what you have to say about verification.

Here at Verilab, we’re seeing an increase in formal verification being used on client projects. The tools have come a long way, especially with formal “Apps” that focus on some specific activities, increasing automation for formal tasks.

Today’s formal tools are a serious alternative to simulation for many functional verification tasks. A strong understanding of the terminology, techniques and general tool capabilities is key for a successful adoption. Although the formal tools look different to one another and have different strengths and weaknesses, the underlying techniques are the same. The domain terminology used is consistent and there are standard input languages. Most of what you’ll need to learn applies to tools across the board.

Interested in dipping a toe in the water?

We’ve partnered with Doulos to deliver a FREE webinar “Formal Verification - Getting Started with Confidence”, an introductory session highlighting some key concepts. No experience with formal verification is required.

The webinar will be presented on June 17th, 2016. For more details and registration click here:
Formal Verification - Getting Started with Confidence

In Part 2, Alex and Thorsten continue discussing the latest developments with Specman and the ‘e’ language, along with practical use cases. They focus on coverage driven distribution and how anonymous methods can be applied. Part 1 of the conversation can be viewed here.

Alex Melikian: Okay. Moving on to another topic, let’s talk about something introduced at a recent conference covering Specman: the notion of coverage driven distribution. This has been something that’s been in the works for some time, now. It’s not 100% complete yet, but it looks like Specman features supporting coverage driven distribution are becoming piece by piece available. Before we get into that, once again for the readers that are not familiar with it, can you explain what are the concepts behind coverage driven distribution?

Thorsten Dworzak: Yes. So the typical problem for coverage closure in the projects we are usually working on as verification engineers is that you have this S curve of coverage completeness. You start slowly and then you easily ramp up your coverage numbers or your metrics to a high number like 80/90 percent.

And then in the upper part of the S curve it slows down because you have corner cases that are hard to reach, etc., etc. And it takes a lot of time to fill the gaps in the coverage over the last mile. So people at Specman have done some thinking about it. And of course one of the ideas that has been around in the community for some time is that you look at your coverage results and feed them back into the constraints solver.

But this is a different approach. Here you look at the actual coverage implementation and derive your constraints from this, or you guide your constraints from your actual coverage implementation. So to give an example, you have an AXI bus and an AXI transaction comprising of an address, a strobe value, direction, and so on. And in your transaction based coverage you have defined certain corner cases like hitting address zero, address 0xFFFF and so on. And whenever Specman is able to link this coverage group to the actual transaction, which is not easy and I’ll come to that later – then it can guide the constraints solver to create higher probability for these corner cases in the stimulus.
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At Verilab, we like to have plenty of discussions centered on verification. Recently, some chatter came up about the possibilities of where verification could be headed in the near future. This prompted Verilab consultants to start a discussion on what they thought the future of verification would hold. This was not so much a look into crystal balls and making predictions, but rather an attempt at understanding what new verification methods and technologies may transpire in the coming years, based on our recent collective experience.

This subject was left intentionally vague with the objective to get as much diversity in perspective and opinion as possible. What materialized was a set of very interesting points covering multiple fronts: tools, languages and industry practices.

Breaking away from our usual interview style, this edition of “Thoughts on Verification” will invite our readers to be a fly on the wall within Verilab, as we share some of the key points and perspectives brought up in this discussion. As our readers would agree, predicting the future is not an easy task, nor an accurate one. With that in mind, here’s a summary of what our consultants thought people involved with verification should look out for in the near future.
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Mark Litterick’s OCP-IP December 2008 newsletter article demonstrates how two key aspects of OCP – profiles and transactions — were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems.

The article uses the Verilab OCP uVC as an example. This uVC is a mixed-language OCP compliant verification component that supports a major subset of Open Core Protocol Specification 2.2. The OCP uVC is implemented using SystemVerilog and e verification languages and complies with both the Open Verification Methodology (OVM) and e Reuse Methodology (eRM). The verification component can be used in SystemVerilog only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular eVC.

The OCP-IP article can be downloaded here

The full whitepaper can be downloaded here