Mark Litterick, Jason Sprott and Jonathan Bromley will be presenting the their “Advanced UVM Tutorial - Taking Reuse To The Next Level” in two sessions on Day 1 (Wednesday 11th Nov).

Full details of the tutorial are in this abstract: verilab_dvcon_eu2015_abstract

Jonathan Bromley will be presenting a paper he co-authored with Kevin Jonhston on Day 2 (Thursday 12th Nov) in the

Session TA1: Advanced Verification & Validation – 1 Forum 1

TA1.1: Is Your Testing N-wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus

Abstract:
Pairwise, and more generally N-wise, pattern generation has long been known as an efficient and effective way to construct test stimulus and configurations for software testing. It is also highly applicable to digital design verification, where it can dramatically reduce the number and length of tests that need to be run in order to exercise a design under test adequately. Unfortunately, readily available tools for N-wise pattern generation do not fit conveniently into a standard hardware verification flow. This paper reviews the background to N-wise testing, and presents a new open-source SystemVerilog package that leverages the language’s constrained randomization features to offer flexible and convenient N-wise generation in a pure SystemVerilog environment.

A freely downloadable SystemVerilog code package, together with the paper and presentation describing it will be available after the conference is over.

Verilab will be participating in SNUG Canada on Thursday 1st October.

Bryan Morris will re-present his paper entitled “RESSL UVM Sequences to the Mat” that he co-authored with Jeff McNeal (which won the 2014 SNUG SV Technical Committee’s Best Paper award) in the A1 - User Session - Testbench Techniques with UVM session.

Alex Melikian will present his paper, co-authored with Hilmar Van Der Kooij and entitled “Replacing Hardcoded Register Values with Hardcore Abstraction” in the same session.

Bryan and Alex will be available to discuss their papers at the SNUG Pub following the end of the afternoon’s technical sessions.

[updated: Alex and Hilmar's paper and slides can be found on our resources page. ]

Verilab will be at the Designer Community Expo where we will be raffling an Amazon Echo.

On Friday September 18th, Kevin Johnson will be presenting in the FA3 Verification - Improving Test Generation session a paper co-authored with Jonathan Bromley entitled Is Your Testing N-Wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus.

Jeff Montesano will be presenting the Technical Committee Award Winner during the FB4 User & Tutorial Session - UVM Agents, Verdi Debug session a paper co-authored with Mark Litterick entitled Mastering Reactive Slaves in UVM.

Papers and presentations for both can be downloaded from the Papers and Presentations section of our website.

Verilab’s CTO, Jason Sprott will be giving a presentation co-authored with Cadence’s John Brennan entitled Predicting Verification Closure of IP Designs.

Jason will be in Room 101 at 52nd DAC next Tuesday June 9^th presenting about how verification closure of IP designs can be both predictable and deterministic. Harnessing the power of big data, a prediction engine will be described which allows metadata from previous projects to be used to forecast all the key metrics for the current project.

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Verilab consultant Jeff McNeal presented a paper he co-authored with Bryan Morris entitled “RESSL UVM Sequences to the Mat”.

A copy of the paper, presentation and source-code is available on our website under the Papers and Presentations category of the resources section.

Verilab will be at the Designer Community Expo at SNUG SV on Monday March 23^rd between 4 and 8 pm. We’ll be giving away a GoPro Hero camera and accessories. Stop by and ask about our verification consulting and contracting services, or just to chat about verification in general.

On Tuesday March 24^th at 1:30, Jeff McNeal will be presenting a paper co-authored with Bryan Morris entitled “RESSL UVM Sequences to the Mat” in the Verification 2 track. Come in early, as he will be presenting just after the Technical committee’s Best Paper winner.

Once again, Verilab had several people present at DVCon 2015. All of the papers and presentations have been posted here on the Verilab website.

Mark Litterick, presented his paper entitled Lies, Damned Lies and Coverage. The slides for Mark’s presentation can be downloaded here: Lies, Damned Lies and Coverage - slides. Mark’s paper won an Honorable Mention in the Best Paper category.

Paul Marriott presented a paper co-authored by Jason Sprott and Matt Graham (of Cadence Design Systems) entitled Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling. The slides for Paul’s presentation can be downloaded here: Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling - slides

Jonathan Bromley presented a paper entitled Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation. The slides for Jonathan’s paper can be downloaded here: Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation - slides

Come and join us at DVCon 2015 in San Jose, CA, from March 2^nd - 5^th. Several of us from Verilab will be presenting.

Papers:

• Wednesday March 04
  • Session 10 10:00am - 11:30am | Monterey/Carmel | Paper 10.2 Lies, Damned Lies, and Coverage by Mark Litterick
  • Session 11 2:30pm - 4:30pm | Oak | Paper 11.4 Double the Return From Your Property Portfolio: Reuse of Verification Assets From Formal to Simulation by Jonathan Bromley
  • Session 13 2:30pm - 4:30pm | Monterey/Carmel |  Paper 13.4 Navigating the Functional Coverage Black Hole: Be More Effective at Functional Coverage Modeling by Jason Sprott, Paul Marriott and Matt Graham (Cadence inc)

Verilab is also sponsoring the best paper and poster awards this year. Good luck to all the participants, we hope to see you there!

Several folks at Verilab presented material at DVCon 2014. All papers and presentations have now been posted here on the Verilab website.

Mark Litterick presented his paper, authored with Marcus Harnish, paper entitled Advanced UVM Register Modeling - There’s More Than One Way to Skin A Reg. The slides for Mark’s presentation can be downloaded here: Advanced UVM Register Modeling Slides

Paul Marriott presented a paper authored by Jason Sprott, Gordon McGregor and André Winkelmann entitled A Guide To Using Continuous Integration Within The Verification Environment The slides for this presentation can be downloaded here: Guide To Using Continuous Integration - slides

Jeff Montesano presented a poster he co-authored with Mark Litterick entitled Verification Mind Games - how to think like a verifier and its associated paper can be downloaded here: Think like a verifier paper

Vanessa Cooper presented a poster she co-authored with Paul Marriott entitled Demystifying the UVM Configuration Database and its associated paper can be downloaded here: Configuration Database demystification paper

Come and join us at DVCon 2014 in San Jose, CA, from March 3^rd - 6^th. Several of us from Verilab will be presenting.

Papers:

• TUESDAY March 04
  • Session 4 3:00pm - 5:00pm | Oak Ballroom | Paper 4.3 SystemVerilog, Batteries Included: A Programmer’s Utility Library for SystemVerilog by Jonathan Bromley and André Winkelmann
• WEDNESDAY March 05
  • Session 9 10:00am - 11:30am | San Jose/Santa Clara Ballroom | Paper 9.1 Advanced UVM Register Modeling - There’s More Than One Way To Skin A Reg
    by Mark Litterick and Marcus Harnish
  • Session 10 3:30pm - 5:00pm | Oak Ballroom | paper 10.1 A Guide to Using Continuous Integration Within the Verification Environment by Gordon McGregor (Nitero Inc.), Jason Sprott, and André Winkelmann

Posters:

• TUESDAY March 04 Poster Session 10:30am - 12:00pm | Gateway Foyer
  • Poster 1P.10 Demystifying the UVM Configuration Database by Vanessa Cooper and Paul Marriott
  • Poster 1P.15 Verification Mind Games - How to Think Like a Verifier by Jeff Montesano and Mark Litterick

Verilab is also sponsoring the best paper and poster awards again this year.