Alan Naumann, President and CEO, CoWare, gave the second portion of the keynote this morning at DATE, entitled “Was Darwin Wrong? Has Design Evolution Stopped At the RTL Level? Or Will Software and Custom Processors (Or System-Level Design) Extend Moore’s Law?” Phew. The title of the talk was just about as long as Alan’s defense of the point that current problems in chip design are just like global warming and the extinction of the dinosaurs. On the bright side, Alan highlighted several key changes occurring in chip design and proposed long term solutions in order to stave off our collective extinction.

For example, in the past, new products ramped slowly into the market until reaching maturity after 3-5 years, and then gradually were end of life’d at a planned pace. These days, new products experience a tremendously fast ramp-up and quickly reach the end of their usefulness after approximately a year. That means that companies need to churn out new products much faster than ever before.

In addition to faster product ramps, projects today require significantly more investment in software development. According to Naumann, in 1997, a typical mobile phone had about 200K lines of code (LOC). In 2005, that number had jumped to 2.5M LOC!

Another interesting trend? Between 1985 and 2005, Naumann claimed the number of hardware engineers has increased by about 1.5-2x. In that same time, ASIC starts have dropped by an order of magnitude or more, and the number of embedded software engineers has skyrocketed.

So what do we need to do in order to deal with all of these changes in the chip design landscape? First, Naumann stated that individual engineers need to learn to model at a higher level of abstraction. Engineering teams need to differentiate their products using software and new architectures. Companies need to adjust in the way they work with vendors to be more of a partnership, and (of course) need to provide virtual models to customers in advance of real implementations.

A Random Presenter and Panelists Before the DATE Keynote
Originally uploaded by brillianthue.

It’s been a busy first day at DATE. The morning kicked off with keynote addresses given by Dr. Tohru Furuyama, General Manager, Center of Semiconductor Research and Development at Toshiba and Alan Naumann, President and CEO, CoWare. Tohru’s talk, entitled “Challenges of Digital Consumer and Mobile SoC’s: More Moore Possible?” was heavily technical for a keynote and focused on the need for Electronic System Level (ESL) tools and methodologies in order to keep up with increasing design complexity in the SoC market.

According to Furuyama, development costs are increasing rapidly with the advent of each new manufacturing technology, and costs have soared from between $8M to $50M to develop a chip from scratch. In order to reduce cost and decrease time to market (TTM) he claims it is necessary to adopt a strategy of developing system models in advance of the availability of RTL or silicon so that schedules for the software and hardware teams can overlap. To prove his point, he cited internal project experience suggesting that it took about 130 days after first samples returned from the fab to debug software before Toshiba started using system level modeling, and only 41 days after. Furuyama felt that was a significant improvement, and so do I!

Furuyama also proposed taking advantage of behavioral synthesis techniques to speed hardware development and simulation times. Experience at Toshiba suggests that C models can provide a 5-10x improvement in simulation performance over RTL. Additionally, the performance of synthesized designs was found to be very close to that of manually written RTL, though the gate count was potentially higher.

I was surprised at the amount of technical detail that Dr. Furuyama went into during his talk, but it was interesting to hear. The moral of the story? Use ESL tools and methodologies in order to save development time and reduce project costs. Perhaps one of our astute readers can comment on whether the results Dr. Furuyama described have been seen elsewhere.

Thanks for stopping by! Jason Sprott, Terry Lawell, and JL Gray from Verilab will be attending the Design Automation and Test conference in Europe April 16-20, 2007. We will be posting information about the conference here on this site and on Cool Verification throughout the week. Check back often to see what we’ve been up to!