Over 50% of chip designs today have >20 clock domains. This makes CDC verification pretty high up on the priority list. At Verilab we have our own CDC workshop, which is split into a design portion (it’s better to get CDC design right in the first place), and a verification portion, which focuses on using SystemVerilog Assertions and dynamic simulation. This gets our clients hitting the ground running with CDC really quickly, using the tools they have at their disposal today. However, we’re always on the lookout for other cool CDC verification techniques. I got an update yesterday of 0-IN’s CDC verification capabilities and they still look pretty good.

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I was feeling a bit jet lagged today at DAC – nothing to do with the wine the evening before – so I decided to visit the Oxygen Party Bar installed at the Mentor Graphics booth. The friendly “bar staff” were only too happy to advise me that a 10 minute shot of the 90 percent concentration of aroma-scented oxygen, would give me “immediate relief”.

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We made it through our first day at DAC 2007. It has been several years since I last visited DAC, but it did not seem to be as well attended this year. Aside from that, I saw a lot of new companies, many of which are start-ups trying to find their place in the EDA world. It is mind boggling to see how many companies are evolving to address the many complex design and verification tasks.
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Power-aware design and verification is a hot topic this year at DAC. I attended the “Design and Verification of Low Power ICs” workshop on Sunday, which mainly focused on Version 1.0 of Accellera’s Unified Power Format (UPF) Standard. The thing I was particularly interested in was how (if at all) UPF could help us functionally verify power-aware logic at the RTL level. If bugs can be found in power implementation at the RTL level, it is far more cost effective and practical than trying to find them at gate-level, or later. The workshop included of a number of presentations from different EDA vendors illustrating how UPF can be used to do just that.
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Today I had the opportunity to meet with Sean Smith, Chief Verification Architect, and Tim Cook, Staff Software Engineer at Denali. Sean and Tim were kind enough to spend an hour and a half discussing SystemRDL, Blueprint, and PureSpec SystemRDL with me. For those of you unfamiliar with these products, they cn be summarized as follows:

• SystemRDL - A specification language for describing control and status registers (CSRs).
• Blueprint – A tool that takes a register set described in SystemRDL and transforms it into the appropriate documentation and data structures required for design, verification, and software development.
• PureSpec SystemRDL – Verification IP designed to allow users to abstract the way registers are accessed and to provide a set of sequences that can be used to test CSRs in a variety of ways.

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I had one of those “Doh! Why didn’t I think of that?” moments at the Mentor booth today. Mentor have a new tool [1] in the pipe called InFact which solves a problem in stimuli generation that you might not even have realised you had [2]. Once it’s pointed out to you, you might start wondering why you put up with it for so long.

Have you ever run a regression and found it took ages to hit those last few functional coverage points? For example, you fully define your AHB transaction, but you never seem to hit that weird WRAP8 BUSY 16bit OPCODE scenario. No matter how many tests you run, it just never seems to get hit, although you’ve hit some other scenarios a million times.

That seems like a bit of a waste of time.
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Yep - that’s right. Gary Smith announced it this morning at DAC. Now it might come as a surprise to those of us who are working in the area of hardware verification, but apparently it’s true. It certainly came as a surprise to me, and to a friend of mine who’s the manager of a hardware team, but perhaps we just have a different interpretation of “under control”. Those of us deep in the verification trenches might say a lot of things about the state of verification today, but I’m not sure “under control” would be one of them
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This week at DATE Morgan Kaufmann Publishers have announced a release date of August 2007 for the US and September 2007 for Europe of Verilab’s very own David Robinson’s new book, “Aspect-Oriented Programming with the e Verification Language - A Pragmatic Guide for Testbench Developers”. The book:

• Introduces and explains a complex topic using familiar terms and examples
• Will cause many daily coding problems to vanish and allow you to focus on your real job of verifying hardware designs
• Takes a pragmatic approach to this complex subject.. “do it this way, because it works…”

Information about how to order a copy will be announced as soon as it is available.

According to a helpful representative at the Synopsys booth this afternoon, VCS supports 99% of the SystemVerilog Testbench features. Which 99%? I’m aware it doesn’t support parameterized classes or the shuffle() method for arrays. I’m sure there must be more features as well. Also, a heads up. While browsing through the VCS documentation recently I discovered documentation on AOP extensions for SystemVerilog built into VCS. I haven’t tried it out yet to see if it works. However, as with Vera, the AOP support is nothing like the “when inheritance” found in Specman/e. When Inheritance allows fields, methods, and additions to methods to be added into an instance of a class only when a given field has been randomly set to a specified value.

Also useful to know? The 2006.06-12 release of VCS fixes several bugs in the graphical debugger (DVE) related to SystemVerilog.

Tuesday afternoon I attended the Cadence/Doulos solutions workshop entitled “Adopting a Plan-to-Closure Methodology across Design Teams and Verification Teams”. The session was presented by Hamilton Carter from Cadence, co-author of the soon to be released book “Metric Driven Design Verification”, and Dave Long from Doulos. Hamilton focused much of his portion of the session on verification planning and functional coverage. I’m sure much of the information from his talk will be covered in his book, but there were a few things that stood out.

Hamilton stressed the importance of planning sessions and the idea of creating a prioritized set of metrics. He also highlighted the value of the verification planning document (vPlan). I asked him later in the presentation if it was possible to put too much emphasis on the vPlan to the point where it was being held up to the exclusion of other sets of metrics that should be used together with the vPlan to get an accurate picture of where the project is going (think bug count, number of recently changed lines of code, real progress in completing assigned tasks, etc). According to Hamilton, the Cadence methodology doesn’t take these things into account yet, but he did mention that tools such as Enterprise Manager may have some point be integrated with LSF and Clearcase to the point where you could automatically extract such information.

Next up was Dave Long. Dave’s description of uRM was the first I’ve seen any details about how the methodology has been applied to SystemVerilog, and my first impression is that the results aren’t good (yet). First of all, Incisive does not yet support class-based test environments, only module-based ones. That may change soon, but seems to be a current limitation. Second, sequences, one of the more widely used features of the eRM (the predecessor to uRM focused on the e language), seems basically useless when implemented in SystemVerilog. The implementation relies on creating a driver with one task corresponding to each of what would have originally been an individual “when subtype” of a sequence. The first thing I would do if I was stuck using that feature would be to throw it away and code a more customizable solution (perhaps using factories?). The problems with the feature would be especially severe when dealing with verification IP. Currently in ‘e’ it is possible to override default sequences and add new ones very easily. With this new approach the best possible outcome would be for a user to extend the original driver and hope it was possible to instantiate it in place of the base class in the verification IP.

One other item of note - if I understood correctly there have been no announced improvements to Cadence SystemVerilog support or the uRM. There may be some smaller announcements in the near future, but it doesn’t appear that anything major will be revealed for the next several months at least.