We made it through our first day at DAC 2007. It has been several years since I last visited DAC, but it did not seem to be as well attended this year. Aside from that, I saw a lot of new companies, many of which are start-ups trying to find their place in the EDA world. It is mind boggling to see how many companies are evolving to address the many complex design and verification tasks.
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Power-aware design and verification is a hot topic this year at DAC. I attended the “Design and Verification of Low Power ICs” workshop on Sunday, which mainly focused on Version 1.0 of Accellera’s Unified Power Format (UPF) Standard. The thing I was particularly interested in was how (if at all) UPF could help us functionally verify power-aware logic at the RTL level. If bugs can be found in power implementation at the RTL level, it is far more cost effective and practical than trying to find them at gate-level, or later. The workshop included of a number of presentations from different EDA vendors illustrating how UPF can be used to do just that.
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Today I had the opportunity to meet with Sean Smith, Chief Verification Architect, and Tim Cook, Staff Software Engineer at Denali. Sean and Tim were kind enough to spend an hour and a half discussing SystemRDL, Blueprint, and PureSpec SystemRDL with me. For those of you unfamiliar with these products, they cn be summarized as follows:

• SystemRDL - A specification language for describing control and status registers (CSRs).
• Blueprint – A tool that takes a register set described in SystemRDL and transforms it into the appropriate documentation and data structures required for design, verification, and software development.
• PureSpec SystemRDL – Verification IP designed to allow users to abstract the way registers are accessed and to provide a set of sequences that can be used to test CSRs in a variety of ways.

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I had one of those “Doh! Why didn’t I think of that?” moments at the Mentor booth today. Mentor have a new tool [1] in the pipe called InFact which solves a problem in stimuli generation that you might not even have realised you had [2]. Once it’s pointed out to you, you might start wondering why you put up with it for so long.

Have you ever run a regression and found it took ages to hit those last few functional coverage points? For example, you fully define your AHB transaction, but you never seem to hit that weird WRAP8 BUSY 16bit OPCODE scenario. No matter how many tests you run, it just never seems to get hit, although you’ve hit some other scenarios a million times.

That seems like a bit of a waste of time.
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Yep - that’s right. Gary Smith announced it this morning at DAC. Now it might come as a surprise to those of us who are working in the area of hardware verification, but apparently it’s true. It certainly came as a surprise to me, and to a friend of mine who’s the manager of a hardware team, but perhaps we just have a different interpretation of “under control”. Those of us deep in the verification trenches might say a lot of things about the state of verification today, but I’m not sure “under control” would be one of them
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