Several folks at Verilab presented material at DVCon 2013. All papers and presentations have now been posted on the Verilab website.

Mark Litterick won the best paper award for his paper entitled SVA Encapsulation in UVM - Enabling Phase and Configuration Aware Assertion

The slides for Mark’s presentation can be downloaded here: SVA Encapsulation Slides

Paul Marriott presented a poster entitled Run-time Configuration of a Verification Environment - A Novel Use of the OVM/UVM Analysis Pattern and the associated paper can be downloaded here: Run time configuration paper

Mark also presented a poster entitled Pragmatic Verification Reuse in a Vertical World and its associated paper can be downloaded here: Pragmatic reuse paper

As well as winning best paper and presenting a poster, Mark also gave his thoughts on OVM to UVM Migration - or There and Back Again, a Consultant’s Tale which formed part of the tutorial on Lessons from the Trenches: Migrating Legacy Verification Environments to UVM

Peggy Aycinena wrote an interesting piece on Jason Sprott’s participation in the Cadence-sponsored luncheon panel on Best Practices in Verification Planning.

Finally, check out Richard Goering’s writeup of JL Gray’s Industry Leaders Panel: “The Road to 1M Design Starts”

Verilab’s Bryan Morris will be presenting his paper “Yes We Kanban: An Introduction to an Agile Management Technique” at the Wednesday March 13th, Session VER204 of CDNLive Silicon Valley 2013.

This presentation provides an overview of the Kanban technique and guidance on how you can start to use it in your team’s ASIC/FPGA development flow.

The key advantages of using Kanban are that it provides a visual overview of what your team is working on, clearly identifies current blocking issues and bottlenecks in your process, and creates opportunities for the team to proactively discuss their processes and resolve any blocking issues.

Come join us at DVCon 2013 in San Jose, CA. Several of us from Verilab will be involved in the following activities:

• Monday February 25th, Tutorial Lessons from the Trenches: Migrating Legacy Verification Environments to UVM™ Mark Litterick presenting
• Tuesday February 26th, Poster session Paul Marriott presenting “Run-Time Configuration of a Verification Environment – A Novel Use of the OVM/UVM Analysis Pattern” and Mark Litterick presenting “Pragmatic Verification Reuse in a Vertical World”
• Tuesday February 26th, Paul Marriott is chairing the REGULAR SESSION: Case Studies - I
• Wednesday February 27th “Session 11 - Hardcore UVM-II” Mark Litterick presenting “SVA Encapsulation in UVM - Enabling Phase and Configuration Aware Assertion”
• Wednesday February 27th Luncheon Best Practices in Verification” Jason Sprott, panelist
• Wednesday February 27th JL Gray moderates Industry Leaders Panel: The Road to 1M Design Starts

Verilab is also sponsoring the Best Paper and Poster Award.

With the 49th DAC almost upon us, design and verification engineers will inevitably be thinking of the latest and greatest tools on offer from the EDA vendors. Despite complaints of ever increasing complexity being a problem, somehow the tools we’ve been using for the past several decades have been good enough to allow Moore’s Law to continue unabated, with 22nm technology being the latest production point on this exponential curve. Verilab will be there, as usual, to cover this important event and our VP and blogger-in-chief, JL Gray will be covering this over on Cool Verification.

As much as new shiny tools are interesting, sometimes it’s interesting to focus on some more mundane aspect of verification. Often verifiers are faced with what appears to be a simple problem, but which isn’t implemented in any vendor-neutral methodology. It’s always tempting to use tool-specific code, but fewer companies have the ability to restrict themselves to only one vendor over the lifetime of a product and its subsequent revisions. This is where methodologies such as the UVM are particularly useful. However, as much as they are touted as the solution to today’s verification problem, they often are missing some features which make a verifier’s job easier.

One such example is the ability to monitor value changes on arbitrary signals in the DUT without having to have a lot of hard-coded cross-module references. Such references make re-usability difficult, either when a block is reused in a top-level environment or in a completely different environment altogether. It would be nice if such references could be simply specified as strings and then advantage could be taken of the UVM’s configuration database to set and appropriate string for the use-case in question. However, such a facility is not part of the UVM right now.

Fortunately, Verilab’s Jonathan Bromley was motivated enough, when faced with this problem in a real project, to come up with a novel package that uses the SystemVerilog VPI/DPI to neatly provide a solution that works in the three major simulators that support the UVM. Jonathan  presented his paper on this at SNUG Munich on May 23rd and at SNUG UK on May 24th. His paper received the Technical Committee’s “Best Paper Award”.

Just a quick FYI… both David Robinson and I have posted our DAC presentations on Verification Planning and SystemVerilog Interoperability on the Verilab website. Please check them out and let us know if you have any questions or comments!

I just saw the announcement for CDNLive! Silicon Valley, to be held September 10-12 in San Jose. I’d encourage you to attend. I had the opportunity to attend CDNLive! Europe in May and found it refreshing for a regional vendor-led conference to pack so much good material, interesting people and effective knowledge sharing into 3 days. There were over 550 attendees. The venue was great and the tone was appropriately ‘real’ for a developers’ conference.

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Thursday morning at DAC I had the opportunity to speak with Larry Lapides, VP of Worldwide Sales for Averant about formal verification and Averant’s formal verification product Solidify.  Averant’s formal tools compete with those from Jasper, OneSpin, Cadence, and Synopsys, among others. 

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Denali Night Fever 2007

Music.  Dancing.  Free food and drink.  Did I mention drink?  All in a room full of engineers…?  As it turns out, Denali Night Fever provided an excellent opportunity for a veritable who’s who of EDA luminaries and the rest of us just along for the ride to relax after a couple of long days at the DAC.  The event was held at the On Broadway Event Center just a few blocks away from the San Diego Convention Center.  Music was provided by Full Disclosure Blues featuring Gary Smith and Aart de Geus, and Cadence’s Ted Vucurevich with The Chad Tuckers.  Everyone’s favorite industry gadfly John Cooley was also present, earplugs and all, to serve as the judge of the “EDA Idol” competition. 

The party itself was a blast, but the more interesting question is whether the same held true for DAC this year.  According to Richard Goering, there were 5,135 registered attendees, 3,796 exhibitor attendees, and 400 “other” attendees, for a total of 9,331 people.  These numbers are down significantly from last year’s DAC in San Francisco, where presumably everyone and their dog went to the show as it was driving distance away, but they are also down slightly from the last DAC held in San Diego in 2004. 

Richard’s take was that there wasn’t much exciting going on this year at DAC, but I would tend to disagree.  All four of us from Verilab who attended the conference were able to attend interesting product demos and sessions, and met up with people we otherwise would have had to travel far and wide to see.  It also gave us a chance to catch up ourselves, as there were Verilab attendees from the UK and US who don’t always have the opportunity to meet face to face. 

Some of the info at the conference could have been gleaned from attendance at DVCon or DATE.  The technical sessions at DVCon were consistently the most relevant to my role as a verification consultant.  Its smaller size (710 attendees) made it a good “starter conference” to help kick off the season.  DATE was good because it gave me the opportunity to catch up with current/former clients and colleagues of mine in Europe, and to get a better understanding of what the design and verification community in Europe is interested in, but the technical sessions were far too academic for my taste.  DAC, on the other hand, was a networking paradise.  A large number of people I wanted to see were there, including some unexpected surprises.  I also broadened my horizons a bit more when looking at product demos and was able to catch some interesting stuff I’d missed at the previous conferences. 

Is DAC still relevant?  For me, the answer is yes.  Your mileage may vary.  If you’ve never been to any of the major conferences (a situation I found myself in before this year), you’re missing out.  My horizons have broadened significantly over the last few months.  I’ve got a much better appreciation for the state of the industry, what tools and methodologies are available, and who to call if I need a helping hand than I did back at the beginning of February.

After the keynote on Tuesday I had the opportunity to meet Soha Hassoun, an Associate Professor of Computer Science at Tufts University, while snapping a photo of Steven Levitan (DAC conference chair). Among other things, Soha is involved with a company called Carbon Design Systems. Now, as it turns out I’ve been bombarded with emails from Georgia Marszalek from ValleyPR about Carbon, but for some reason I never fully grasped the value of the company’s product after reading an email description. Based on the additional recommendation from Soha I decided to take a look.

Thursday morning I went by the Carbon booth and spoke with Elizabeth Abraham, VP, Consulting Services and Product Marketing. She gave me an overview of Carbon’s Virtual System Prototype (VSP) software. VSP converts “Verilog, VHDL, and mixed language RTL designs into an ultra-fast, cycle-accurate virtual prototype.” Basically, RTL is converted to high level C software model which can run 10-100x faster than the original design, according to Elizabeth. The other cool feature of Carbon’s product is the ability to debug hardware and software side by side, as bugs tracked down in the generated C code can be mapped back to the original hardware implementation.

I asked Elizabeth how VSP compared with solutions such as the Cadence ISX, which can provide coverage metrics and constrained random testing for embedded software. Based on my understanding of the tools, it appears VSP is focused on verifying the full system hardware/software solution, whereas ISX is focused on testing the interface layer between the system software and hardware (i.e. not the entire software solution). The other difference is that VSP should dramatically speed up simulations whereas ISX would not unless it was paired with a Palladium hardware accelleration box.

I had my first brush with formal methods about 11 years ago when I started my PhD. I was asked to look at the Z language, which would let you write a specification that could be formally proven to be correct. The downside was that, at any given time, there would only be three people on the planet with large enough brains to use it. Part of the complexity of Z was down to the fact that English characters were not allowed (that would have been too easy) - only Greek symbols by the looks of things. I’m not sure how you were meant to type it into a text editor, and I didn’t pursue it far enough to find out.

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