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Archive for the ‘Conferences’ Category

SNUG Austin 2017 – UVM Harness Presentation

Monday, October 16th, 2017 by Alex Melikian

Verilab will lead a strong presence at SNUG Austin 2017, with consultants Jeff Montesano and Jeff Vance presenting “Verification Prowess with the UVM Harness” on Thursday, October 19th.

Based on their paper, the presentation will explore powerful and highly applicable techniques in the domain of testbench to DUT connection, blazing a path towards achieving verification prowess in projects of all levels. Details will be provided showing how any testbench can use the harness to manage connections more easily while allowing you to manipulate the roles of agents without impact to interface connections. Furthermore, demonstrations will be given on how the presented solution allows UVM testbench developers to apply powerful verification strategies that would not be possible with traditional connections.

More details of this presentation, along with other conference details, can be found here:

https://event.synopsys.com/ehome/277997/Agenda/

Verilab looks forward to taking the opportunity and engage with the verification community at conferences like SNUG Austin. All our past published conference papers and presentations can be found here:

http://www.verilab.com/resources/papers-and-presentations/

See you at SNUG Austin 2017!

DVCon Europe 2017 – Formal Verification Tutorial & UVM Multi-Language Presentation

Thursday, October 12th, 2017 by Alex Melikian

Verilab is proud to participate at DVCon Europe 2017 with a tutorial and presentation given by our own Jonathan Bromley and Thorsten Dworzak.

Firstly on Monday October 16th, senior consultant Jonathan Bromley will be giving the “Formal Verification in the Real World” tutorial. Based on our well received foundation level tutorial from the 2016 conference, this year’s session will cover some of the more advanced techniques and workflow patterns on one of the most talked about areas of verification. More details here:

https://dvcon-europe.org/content/event-details?id=234-1-T

Whereas on Tuesday October 17th, principal engineer Thorsten Dworzak will co-present “UVM Multi-Language Library: Hands-On” with Angel Hidalga of Infineon Technologies. The presentation covers their work of developing a simulator independent library extension of the UVM, promising easy integration of different high-level verification languages. More details here:

https://dvcon-europe.org/content/event-details?id=234-5

Verilab looks forward to hearing from the verification community and their thoughts about these or any other verification topics. As always, all our past published conference papers and presentations can be found here:

http://www.verilab.com/resources/papers-and-presentations/

See you there!

Verilab at CDNLive Munich 2017 May 16

Monday, May 15th, 2017 by Paul Marriott

We’re proud to announce Verilab consultant Thorsten Dworzak will be presenting at CDNLive Munich 2017 this Tuesday May 16th.

Thorsten will be presenting his paper, entitled “UVM-ML: Message from the Trenches” in the FV 15 track at 14:30 in the Chiemsee room of the INFINITY Hotel & Conference Resort.

Abstract

The UVM multi-language package version 1.2 and its integration into Cadence IES promise easy integration of different high-level verification languages. We applied it together with previously existing techniques to attach a SystemC model to different UVM-SV testbenches. The interface between the two worlds has been implemented using TLM2, DPI-C, and FMI. Over the course of this project we faced some obstacles and stumbling blocks across different aspects. By sharing our experience and some resulting guidelines, we hope to provide others with a smoother experience.

For the verification of an ARM CPU IP we developed a SystemC model. The model serves two different verification focuses. First, it is used as reference model for the DUT in a fully-featured UVM testbench. The testbench provides stimuli generation, scoreboarding, and coverage. Stimuli generation and scoreboarding are using their own C-model instance with a slightly different feature set. Both model instances receive CPU instructions from the testbench.

Second, it is used as stand-alone instruction-set simulator (ISS), embedded in a UVM testbench that mainly provides shared memory and allows running a set of self-checking assembler tests. This testbench can use either the model or the DUT as a drop-in component. The C-model operates in master mode, i.e. it fetches CPU instructions from the shared memory.

Third, the C-model is going to be used in a software simulator, which determines the performance requirements.

In this publication we will mainly focus on the reference model (scoreboard) use-case.

We look forward to seeing you there.

Verilab at SNUG Ottawa 2017 April 21

Thursday, April 13th, 2017 by Paul Marriott

We’re proud to announce Verilab consultant Alex Melikian will be presenting at SNUG Ottawa 2017 next Friday April 21st.

Alex will present his paper, jointly authored with Paul Marriott, “Perplexing Parameter Permutation Problems? Immunize Your Testbench” at 3:30 in the Verification-I track.

For more information on times and events consult the schedule, or download the SNUG Ottawa mobile app.

To download any of our previous papers and presentation, check out our “Papers and Presentations” page.

We look forward to seeing you there.

DVCon Europe 2016: Slicing Through the UVM’s Red Tape - A Frustrated User’s Survival Guide

Tuesday, October 18th, 2016 by Paul Marriott

Jonathan Bromley will be presenting a paper on Thursday 20th, in session 1 (3:15-4:30PM), examining some of the challenges and frustrations for novice and intermediate-level users of the UVM on real projects.

This paper looks at typical examples of such challenges, and offers solutions that respect fundamental aims of the UVM: consistency, reusability, and expressive power.

If you’ve struggled with the integration of directed tests, external models into the sequences mechanism, reconciling the abstract and the untimed nature of sequences with the need for precise control over stimulus timing, proper use of the configuration database, or working with a parameterized device-under-test, this presentation might be for you.

A full description of the tutorial is detailed in the DVCon Europe 2016 conference program

DVCon Europe 2016: Formal Verification - Too Good To Miss

Monday, October 17th, 2016 by Paul Marriott

Jonathan Bromley and Jason Sprott will be delivering a tutorial on Wednesday 19th October 10:00-11:30AM at DVCon Europe 2016 in Munich.

We find that getting started on formal verification can be a challenge. It’s different to traditional simulation, with some unfamiliar concepts. However, for the right kind of problem, it’s just too good to miss out on due to the lack of experience. This tutorial aims to address that initial lack of confidence and basic knowledge, helping engineers to get started on real project work using formal verification. We’ll be using a small case study to take attendees through the lifecycle of a formal verification project for a block-level RTL design.

A full description of the tutorial is detailed in the DVCon Europe 2016 conference program

Verilab Presentations From SNUG Austin

Thursday, October 13th, 2016 by Paul Marriott

Jeff Montesano and Jeff Vance presented their paper entitled “Configuring a Date with a Model – A Guide to Configuration Objects and Register Models” at SNUG Austin this past September 2016.

The full paper and presentation slide can be downloaded from our resources section: snug2016model.

Jonathan Bromley, Mark Litterick, and Vanessa Cooper’s paper entitled “Effective SystemVerilog Functional Coverage: design and coding recommendations” can also be downloaded from our resources section: snug2016cover. Unfortunately, Vanessa was unable to present this due to sickness, though this paper did win the Technical Committee Honourable Mention Award at SNUG2016UK.

Thanks to all who attended!

All of our papers and presentations can be downloaded from our resources page’s papers-and-presentations section.

Verilab at SNUG Austin 2016

Monday, September 26th, 2016 by Alex Melikian

We’re proud to announce Verilab consultants Jeff Montesano, Jeff Vance and Vanessa Cooper will be presenting at SNUG Austin 2016 this Thursday September 29th.

Jeff Montesano and Jeff Vance will present “Configuring a Date with a Model – A Guide to Configuration Objects and Register Models” in the morning session. In addition, as conference technical chair, J. Montesano will have the pleasure to give a short address and introduce the morning keynote speakers.

Vanessa Cooper will present “Effective SystemVerilog Functional Coverage: Design and Coding Recommendations” in the afternoon session.

For more information on times and events consult the schedule, or download the “SNUG Austin” mobile app.

We look forward to seeing you there and hear what you have to say about verification.

DVCon 2016 Best Paper / Poster Awards

Thursday, March 3rd, 2016 by Paul Marriott

Everyone at Verilab would like to congratulate the winners of the 2016 Best Paper and Poster awards which we were proud to sponsor.

BEST PAPER
1st Place

8.2: Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012
Speaker: Eldon G. Nelson - Intel Corp.

2nd Place

5.1: SystemVerilog Interface Classes - More Useful Than You Thought
Speaker: Stan Sokorac - ARM, Inc.

3rd Place

9.3: Functional Coverage Collection for Analog Circuits – Enabling Seamless Collaboration Between Design and Verification
Speaker:Zhipeng Ye - Texas Instruments, Inc.
Authors:Zhipeng Ye - Texas Instruments, Inc.
Honghuang Lin - Texas Instruments, Inc.
Asad Khan - Texas Instruments, Inc

BEST POSTER
1st Place

4P.32 Marrying Simulation and Formal Made Easier!
Speaker:Lun Li - Samsung Austin R&D Center
Authors:Lun Li - Samsung Austin R&D Center
Durga Rangarajan - Samsung Austin R&D Center
Christopher Starr - Samsung Austin R&D Center
James Greene - Samsung Austin R&D Center
Nitin Mhaske - Synopsys, Inc.

2nd Place

4P.22 Improving the UVM Register Model: Adding Product Feature Based API for Easier Test Programming
Speaker:Krishnan Balakrishnan - Analog Devices, Inc.
Authors:Krishnan Balakrishnan - Analog Devices, Inc.
Courtney Fricano - Analog Devices, Inc.
Kaushal M. Modi - Analog Devices, Inc.

3rd Place

4P.14 How Do You Verify Your Verification Components
Speakers:Neil Johnson - XtremeEDA Corp.
Joshua W. Rensch - Superion Technology

Authors:Joshua W. Rensch - Superion Technology
Neil Johnson - XtremeEDA Corp.

Verilab at DVCon 2016

Thursday, February 25th, 2016 by Paul Marriott

Come and join us at DVCon 2016 in San Jose, CA, from February 29th - March 3rd, 2016.

Verilab’s Vanessa Cooper is this year’s Panel Chair and this is what she has to say about the line-up for 2016:

We had a number of excellent panel submissions to consider this year, and selected two that I think are of particular importance and address issues our audience is concerned with right now. Both panels will be held on Wednesday, March 2.

The first panel, “Redefining ESL” will be moderated by Brian Bailey. They will attempt to define ESL verification, from tools to flows. As they discuss, “How or when can all the disparate pieces be brought together, or is that even necessary?” there will be plenty of angles to consider.

The second panel, “Emulation + Static Verification Will Replace Simulation” will be moderated by Jim Hogan of Vista Ventures. The panel will discuss where it sees the verification paradigm of the future and where it leaves RTL simulation. It promises to be a lively discussion!

Bringing together two distinct groups of experts, I think attendees will be pleased by the different discussions and varying points of view offered by both of panels. We look forward to seeing you at DVCon U.S.!

Mark Litterick will be presenting his paper, entitled “Full Flow Clock Domain Crossing - From Source to Si”,  in the Design and Modeling Approaches session at 9am on Tuesday March 1st. This is the paper’s abstract:

Functional verification of clock domain crossing (CDC) signals is normally concluded on a register- transfer level (RTL) representation of the design. However, physical design implementation during the back-end pre-silicon stages of the flow, which turns the RTL into an optimized gate-level representation, can interfere with synchronizer operation or compromise the effectiveness of the synchronizers by eroding the mean time between failures (MTBF). This paper aims to enhance cross-discipline awareness by providing a comprehensive explanation of the problems that can arise in the physical implementation stages including a detailed analysis of timing intent for common synchronizer circuits.

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