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Verilab at DVCon 2018

Come and join Verilab at DVCon 2018 in San Jose, CA from February 26th to March 1st.

Verilab’s Vice President Vanessa Cooper has once again served as the Panel Chair in order to present two interesting and pertinent discussion topics on Wednesday Feb 28th. The first one, titled “Help! System Coverage is a Big Data Problem” will have panelists explore how Portable Stimulus, formal verification, and emulation can be used to help provide confidence in closing system coverage. The second one, titled “The Right Tool(s) for the Toughest Verification Tasks” will cover and debate which available verification tools are best suited for particular tasks, and why some tools tend to dominate over others.

In addition to the panels, Principal Consultant Jonathan Bromley will also conduct a “Formal Verification in the Real World” workshop on Thursday March 1st. Built on the foundation level tutorial “Formal Verification – Too Good to Miss” presented at DVCon Europe 2017, this workshop will provide a quick ramp-up on the next steps to expand Formal Verification practices on your projects. Furthermore demystifying some of the more advanced techniques that are easy enough to use but often tricky to learn.

Last but not least, Senior Consultant Jeff Vance will present “My Testbench Used to Break! Now it Bends” on Tuesday 27th at 15:00 in the Carmel Room. The presentation will detail a solution that allows your UVM testbench architecture to adapt to different design configurations without impacting interface connections. The result is a reusable testbench that can be migrated to future projects with minimal changes.

As always, we look forward to meeting people and sharing ideas in the verification industry. For our past conference papers and presentation, please consult the Papers and Presentations section of our website.

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