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SNUG Austin 2017 – UVM Harness Presentation

Verilab will lead a strong presence at SNUG Austin 2017, with consultants Jeff Montesano and Jeff Vance presenting “Verification Prowess with the UVM Harness” on Thursday, October 19th.

Based on their paper, the presentation will explore powerful and highly applicable techniques in the domain of testbench to DUT connection, blazing a path towards achieving verification prowess in projects of all levels. Details will be provided showing how any testbench can use the harness to manage connections more easily while allowing you to manipulate the roles of agents without impact to interface connections. Furthermore, demonstrations will be given on how the presented solution allows UVM testbench developers to apply powerful verification strategies that would not be possible with traditional connections.

More details of this presentation, along with other conference details, can be found here:


Verilab looks forward to taking the opportunity and engage with the verification community at conferences like SNUG Austin. All our past published conference papers and presentations can be found here:


See you at SNUG Austin 2017!

4 Responses to “SNUG Austin 2017 – UVM Harness Presentation”

  1. Arun Dsouza Says:

    This was a great paper! I had a question though. I’ve got my harness set up with the recommendation of using input wires for the interface. However, I’m unable to drive the interface using regular procedural code (as would be typical with a VIF). Since these are nets, the LRM suggests that they must be driven with continuous assignments. How do you handle this problem?

  2. Alex Melikian Says:

    Hi Arun, I forwarded your answer to the authors, here’s their response:

    The preferred method is clocking blocks. Other solutions are possible and also work, but clocking blocks are probably most familiar to most people. See the example code at http://www.verilab.com/resources/source-code/ for additional detail. The AHB and APB interfaces are the most fully developed at this time. The clocking block will drive the interface ports while procedural code assigns values via the clocking block the typical way. The example code should always be considered the primary reference, even over code examples in the paper, we will be updating the example code on an ongoing (though intermittent) basis.

  3. Arun Dsouza Says:

    I tried out the ‘Dynamically Swapping RTL and Testbench Stimulus’ method using force but I’m not able to get it to work. I suspect it’s because we’re trying to force a net to itself. Can you help me figure out what I’ve possibly missed?


  4. Warner Vera Says:

    Hi verilab.com administrator, Keep it up!

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