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Archive for October, 2017

SNUG Austin 2017 – UVM Harness Presentation

Monday, October 16th, 2017 by Alex Melikian

Verilab will lead a strong presence at SNUG Austin 2017, with consultants Jeff Montesano and Jeff Vance presenting “Verification Prowess with the UVM Harness” on Thursday, October 19th.

Based on their paper, the presentation will explore powerful and highly applicable techniques in the domain of testbench to DUT connection, blazing a path towards achieving verification prowess in projects of all levels. Details will be provided showing how any testbench can use the harness to manage connections more easily while allowing you to manipulate the roles of agents without impact to interface connections. Furthermore, demonstrations will be given on how the presented solution allows UVM testbench developers to apply powerful verification strategies that would not be possible with traditional connections.

More details of this presentation, along with other conference details, can be found here:

https://event.synopsys.com/ehome/277997/Agenda/

Verilab looks forward to taking the opportunity and engage with the verification community at conferences like SNUG Austin. All our past published conference papers and presentations can be found here:

http://www.verilab.com/resources/papers-and-presentations/

See you at SNUG Austin 2017!

DVCon Europe 2017 – Formal Verification Tutorial & UVM Multi-Language Presentation

Thursday, October 12th, 2017 by Alex Melikian

Verilab is proud to participate at DVCon Europe 2017 with a tutorial and presentation given by our own Jonathan Bromley and Thorsten Dworzak.

Firstly on Monday October 16th, senior consultant Jonathan Bromley will be giving the “Formal Verification in the Real World” tutorial. Based on our well received foundation level tutorial from the 2016 conference, this year’s session will cover some of the more advanced techniques and workflow patterns on one of the most talked about areas of verification. More details here:

https://dvcon-europe.org/content/event-details?id=234-1-T

Whereas on Tuesday October 17th, principal engineer Thorsten Dworzak will co-present “UVM Multi-Language Library: Hands-On” with Angel Hidalga of Infineon Technologies. The presentation covers their work of developing a simulator independent library extension of the UVM, promising easy integration of different high-level verification languages. More details here:

https://dvcon-europe.org/content/event-details?id=234-5

Verilab looks forward to hearing from the verification community and their thoughts about these or any other verification topics. As always, all our past published conference papers and presentations can be found here:

http://www.verilab.com/resources/papers-and-presentations/

See you there!

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