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Verilab at CDNLive Munich 2017 May 16

We’re proud to announce Verilab consultant Thorsten Dworzak will be presenting at CDNLive Munich 2017 this Tuesday May 16th.

Thorsten will be presenting his paper, entitled “UVM-ML: Message from the Trenches” in the FV 15 track at 14:30 in the Chiemsee room of the INFINITY Hotel & Conference Resort.

Abstract

The UVM multi-language package version 1.2 and its integration into Cadence IES promise easy integration of different high-level verification languages. We applied it together with previously existing techniques to attach a SystemC model to different UVM-SV testbenches. The interface between the two worlds has been implemented using TLM2, DPI-C, and FMI. Over the course of this project we faced some obstacles and stumbling blocks across different aspects. By sharing our experience and some resulting guidelines, we hope to provide others with a smoother experience.

For the verification of an ARM CPU IP we developed a SystemC model. The model serves two different verification focuses. First, it is used as reference model for the DUT in a fully-featured UVM testbench. The testbench provides stimuli generation, scoreboarding, and coverage. Stimuli generation and scoreboarding are using their own C-model instance with a slightly different feature set. Both model instances receive CPU instructions from the testbench.

Second, it is used as stand-alone instruction-set simulator (ISS), embedded in a UVM testbench that mainly provides shared memory and allows running a set of self-checking assembler tests. This testbench can use either the model or the DUT as a drop-in component. The C-model operates in master mode, i.e. it fetches CPU instructions from the shared memory.

Third, the C-model is going to be used in a software simulator, which determines the performance requirements.

In this publication we will mainly focus on the reference model (scoreboard) use-case.

We look forward to seeing you there.

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