Verilab is proud to have senior consultant Jonathan Bromley host the “SystemVerilog Jinxed Half My Career” panel at DVCon 2017, on Wednesday March 1st. Jonathan continues to serve on the SystemVerilog IEEE committee and is the author of numerous papers, including the recently published “Slicing Through the UVM’s Red Tape”. We took a moment with Jonathan to preview what this panel will cover and what those planning or thinking of attending should expect.
The title is “SystemVerilog Jinxed Half My Career : Where do we go from here”, which signals this panel will focus on areas of improvement. What are those areas of frustration in SystemVerilog you feel need improvement?
It would be easy to give a “where do I start?” response, and it’s not difficult to come up with a laundry list of desirable SystemVerilog improvements and nit-picky complaints. But this is DVCon, and our very knowledgeable and sophisticated audience deserves better. We have five extraordinarily experienced panelists and I hope we can venture beyond details of the languages and tools we have today, and think creatively about what we can and should hope for in the mid-term future. Many languages have been used successfully to create advanced testbenches - ‘e’, C++, Python, Vlang - but there’s no question that SystemVerilog remains dominant. Why is that? What sort of code will verification engineers be writing in five, ten years’ time?
When I talk with young engineers coming in to our field, I increasingly find that they are from a computer-science or software background, and they often become impatient with what they see as the primitive tools and techniques we verification engineers choose to deploy. What’s that all about? Are we verifiers really so backward-looking and ignorant?
Maybe those up-and-coming youngsters don’t quite understand all the problems that we face and we’ve had to solve. Or, maybe, they can bring new ideas and insights that can help us overcome the staggering verification challenges that are yet to come. The panel will be the perfect opportunity for our industry veterans to take questions from DVCon delegates with a wide range of views and experience.
Would this panel include discussions related topics to UVM and as well?
It’s pretty difficult to talk about SystemVerilog for verification without mentioning the UVM. It has made SystemVerilog so much more usable and powerful for verification that we shouldn’t ignore it. However, the UVM is a methodology as well as a toolkit or class library, and it’s capable - in principle - of being used with many different programming languages, not just SV. So I don’t think UVM will be a big focus of our discussion. On the other hand, whenever you’re thinking about any potential replacement for SV, you must at least ask not only whether it can offer an improvement over SV but also whether it can match the power of SV+UVM.
Who will be on the panel?
I’m thrilled to have a terrific lineup of high-profile experts with enormous experience in the verification world. In fact, it’s close to being my personal list of SystemVerilog Superheroes. We don’t have space to do them full justice here, but I hope they will forgive me for these unauthorized thumbnail sketches…
- Arturo Salz was pivotal in bringing the object-oriented testbench features of Vera into SystemVerilog, and has deep experience of design and implementation of SV in simulators.
- Dave Rich must be known to almost everyone in the verification community for his unfailingly insightful papers, articles and forum posts, and he understands the challenges of applying SystemVerilog better than anyone else I know.
- Adam Sherer has huge experience of bringing advanced verification techniques (not just SV!) to the market, and has long been a champion of multi-language solutions.
- Cliff Cummings needs no introduction. For many of us he’s the public face of SystemVerilog, and he’ll bring both his advocacy of SystemVerilog and his deep understanding of the needs and concerns of real users.
- Finally, it’s very exciting to have Phil Moorby on the panel. He created the first Verilog-XL implementation way back in the early 1980s, and has been actively and expertly involved with developments in the language ever since.
Who do you think should attend and what kind of mindset should the audience have walking into this panel?
If you’re attending DVCon at all, you care about verification. If you care about verification, you should sit in on this panel! Our panelists are ready to share their own views about the language so many of us use for verification, whether we love it or hate it.
We hope that will encourage audience members to join the discussion. We’re aiming for more than half the session to be interactive with the audience, and I already know from comments I’ve received privately that there will be plenty of strongly held opinions, passionate support (not only for SystemVerilog!) and challenges to the status quo. Do you still want to be programming in SystemVerilog in ten years’ time? Who knows - ideas shared in this discussion just might shape the future of verification.
Verilab looks forward to meeting all participants and attendees at DVCon 2017. Readers can consult all our past papers and presentations here.