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Archive for October, 2016

DVCon Europe 2016: Slicing Through the UVM’s Red Tape - A Frustrated User’s Survival Guide

Tuesday, October 18th, 2016 by Paul Marriott

Jonathan Bromley will be presenting a paper on Thursday 20th, in session 1 (3:15-4:30PM), examining some of the challenges and frustrations for novice and intermediate-level users of the UVM on real projects.

This paper looks at typical examples of such challenges, and offers solutions that respect fundamental aims of the UVM: consistency, reusability, and expressive power.

If you’ve struggled with the integration of directed tests, external models into the sequences mechanism, reconciling the abstract and the untimed nature of sequences with the need for precise control over stimulus timing, proper use of the configuration database, or working with a parameterized device-under-test, this presentation might be for you.

A full description of the tutorial is detailed in the DVCon Europe 2016 conference program

DVCon Europe 2016: Formal Verification - Too Good To Miss

Monday, October 17th, 2016 by Paul Marriott

Jonathan Bromley and Jason Sprott will be delivering a tutorial on Wednesday 19th October 10:00-11:30AM at DVCon Europe 2016 in Munich.

We find that getting started on formal verification can be a challenge. It’s different to traditional simulation, with some unfamiliar concepts. However, for the right kind of problem, it’s just too good to miss out on due to the lack of experience. This tutorial aims to address that initial lack of confidence and basic knowledge, helping engineers to get started on real project work using formal verification. We’ll be using a small case study to take attendees through the lifecycle of a formal verification project for a block-level RTL design.

A full description of the tutorial is detailed in the DVCon Europe 2016 conference program

Verilab Presentations From SNUG Austin

Thursday, October 13th, 2016 by Paul Marriott

Jeff Montesano and Jeff Vance presented their paper entitled “Configuring a Date with a Model – A Guide to Configuration Objects and Register Models” at SNUG Austin this past September 2016.

The full paper and presentation slide can be downloaded from our resources section: snug2016model.

Jonathan Bromley, Mark Litterick, and Vanessa Cooper’s paper entitled “Effective SystemVerilog Functional Coverage: design and coding recommendations” can also be downloaded from our resources section: snug2016cover. Unfortunately, Vanessa was unable to present this due to sickness, though this paper did win the Technical Committee Honourable Mention Award at SNUG2016UK.

Thanks to all who attended!

All of our papers and presentations can be downloaded from our resources page’s papers-and-presentations section.

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