Everyone at Verilab would like to congratulate the winners of the 2016 Best Paper and Poster awards which we were proud to sponsor.

BEST PAPER
1^st Place

8.2: Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012
Speaker: Eldon G. Nelson - Intel Corp.

2^nd Place

5.1: SystemVerilog Interface Classes - More Useful Than You Thought
Speaker: Stan Sokorac - ARM, Inc.

3^rd Place

9.3: Functional Coverage Collection for Analog Circuits – Enabling Seamless Collaboration Between Design and Verification
Speaker:Zhipeng Ye - Texas Instruments, Inc.
Authors:Zhipeng Ye - Texas Instruments, Inc.
Honghuang Lin - Texas Instruments, Inc.
Asad Khan - Texas Instruments, Inc

BEST POSTER
1^st Place

4P.32 Marrying Simulation and Formal Made Easier!
Speaker:Lun Li - Samsung Austin R&D Center
Authors:Lun Li - Samsung Austin R&D Center
Durga Rangarajan - Samsung Austin R&D Center
Christopher Starr - Samsung Austin R&D Center
James Greene - Samsung Austin R&D Center
Nitin Mhaske - Synopsys, Inc.

2^nd Place

4P.22 Improving the UVM Register Model: Adding Product Feature Based API for Easier Test Programming
Speaker:Krishnan Balakrishnan - Analog Devices, Inc.
Authors:Krishnan Balakrishnan - Analog Devices, Inc.
Courtney Fricano - Analog Devices, Inc.
Kaushal M. Modi - Analog Devices, Inc.

3^rd Place

4P.14 How Do You Verify Your Verification Components
Speakers:Neil Johnson - XtremeEDA Corp.
Joshua W. Rensch - Superion Technology
Authors:Joshua W. Rensch - Superion Technology
Neil Johnson - XtremeEDA Corp.