Congratulations to Jonathan Bromley and Kevin Johnston for winning the “Best Paper” award for their presentation entitled “Is Your Testing N-wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus”.

The full paper is available for download: N-wise paper (PDF)
The presentation is also available for download (complete with speaker notes): N-wise presentation (PDF)

Mark Litterick, Jason Sprott and Jonathan Bromley gave a tutorial entitled “Advanced UVM Tutorial - Taking Reuse To The Next Level”. More details of other tutorials and workshops are available on our Training and Workshops” page, with a full portfolio description. Contact info@verilab.com for more information.

Mark Litterick, Jason Sprott and Jonathan Bromley will be presenting the their “Advanced UVM Tutorial - Taking Reuse To The Next Level” in two sessions on Day 1 (Wednesday 11th Nov).

Full details of the tutorial are in this abstract: verilab_dvcon_eu2015_abstract

Jonathan Bromley will be presenting a paper he co-authored with Kevin Jonhston on Day 2 (Thursday 12th Nov) in the

Session TA1: Advanced Verification & Validation – 1 Forum 1

TA1.1: Is Your Testing N-wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus

Abstract:
Pairwise, and more generally N-wise, pattern generation has long been known as an efficient and effective way to construct test stimulus and configurations for software testing. It is also highly applicable to digital design verification, where it can dramatically reduce the number and length of tests that need to be run in order to exercise a design under test adequately. Unfortunately, readily available tools for N-wise pattern generation do not fit conveniently into a standard hardware verification flow. This paper reviews the background to N-wise testing, and presents a new open-source SystemVerilog package that leverages the language’s constrained randomization features to offer flexible and convenient N-wise generation in a pure SystemVerilog environment.

A freely downloadable SystemVerilog code package, together with the paper and presentation describing it will be available after the conference is over.