Thoughts on Verification: What Does the Future Hold?
At Verilab, we like to have plenty of discussions centered on verification. Recently, some chatter came up about the possibilities of where verification could be headed in the near future. This prompted Verilab consultants to start a discussion on what they thought the future of verification would hold. This was not so much a look into crystal balls and making predictions, but rather an attempt at understanding what new verification methods and technologies may transpire in the coming years, based on our recent collective experience.
This subject was left intentionally vague with the objective to get as much diversity in perspective and opinion as possible. What materialized was a set of very interesting points covering multiple fronts: tools, languages and industry practices.
Breaking away from our usual interview style, this edition of “Thoughts on Verification” will invite our readers to be a fly on the wall within Verilab, as we share some of the key points and perspectives brought up in this discussion. As our readers would agree, predicting the future is not an easy task, nor an accurate one. With that in mind, here’s a summary of what our consultants thought people involved with verification should look out for in the near future.
UVM and Its future
- “The next 1 to 3 years is hardly ‘the future’, but I think it’s the timeline where I would see many verification teams fully adopt today’s UVM best practices”.
- “I agree, I can see teams perfecting true module-level to SoC vertical reuse”
- “We’ll see more UVM add-ons along the lines of uvm_reg. Things like uvm_interrupt or uvm_pads. UVM has become standardized enough that we can build more things on top of it to solve common problems.”
- “I think we will see attached UVM libraries growing more and more into domain specific solutions. Kind of like our own svlib. That’s what the software world did, they built more and more specific libraries and frameworks for the recurring tasks.”
Best Known Methods (BKMs) in Verification
- “Verification will continue to steal BKMs from the software space. Things like continuous integration and distributed revision control will become more commonly adopted.”
- “I can see unit-testing or Test Driven Development (TDD) becoming almost mainstream within 5 years. Not sure what the catalyst will be, but something will click.”
- “VIP or reusable modules can very well be the catalyst for the use of TDD. The functionality of these things is often completed in pieces, aligned with how TDD is used.”
- “I think another area we’ll see develop is verification quality control. What I mean by this is tools and methods that highlight reachable holes, dead code, or problems with checks in the test bench. Verification engineers are human, and they can also make mistakes.”
- “Speaking of checks, I see a need for automated visualization of checks and coverage implementation. Currently, only those intimate with the test-bench or a VIP can locate and describe them.”
Emergence of Formal Verification
- “A few years from today, the use of formal technology will be almost mandatory for anyone in ASIC verification, at least at the block level.”
- “We’re definitely seeing formal verification gain a more important part in coverage analysis, especially at the micro-architecture level.”
- “I see more attention on the cooperation between formal and dynamic methods - something more standardized than the ad-hoc methods of today”
Accessibility to Verification
- “The divergence between design and verification engineers will continue to grow, and at a faster pace. We’ve seen some initial effort, but more work will be done to bridge this gap”.
- “A lower knowledge barrier to entry for verification would be beneficial for the industry. I’ve known people who had interest and a proper mind-set for verification, but lack the resources and exposure to opportunities to learn what is needed. This includes experienced RTL designers as well as fresh university graduates.”
- “We were talking earlier about formal methods. I think the current smartphone-like ‘app-ification’ is making it more accessible to people without extensive verification experience.”
Alternatives to Constrained-Random
- “I foresee a general move by vendors towards methods like computed-graph based testing or coverage-aware stimulus generation. As we’ve talked about, constrained-random can burn a lot of CPU cycles for limited gain, especially when one gets closer to 100% coverage.”
- “Some sort of automatic functional coverage validation for correctness, consistency and completeness will come up. Today these are all completely done manually.”
- “The same can be said for test scenario generation. Some automation does exist, but it’s still in its infancy”
Open Source Verification Languages
- “Open source was one of the biggest game changers in software. I am not sure if the hardware community is too small for open source to thrive or not”
- “We already have a few open source initiatives, but they’re not panning out. Maybe some kind of sponsor will turn up to spearhead these further.”
- “I believe demand for an open source solution will grow. The biggest reason why those not having adopted advanced verification is because their products were not complex enough to justify its cost. Market forces are changing that. They will be eventually forced to adopt, and an open source solution would be the most feasible and economic option.”
And there you have it.
In summary, our consultants appear to have a strong consensus about more UVM add-ons, application of software BKMs and formal verification in the foreseeable future. Though there’s less of a consensus, alternatives to constrained-random generation as well as open source solutions can be other potential areas to keep an eye out for.
Whichever may be the case, there’s no doubt between our consultants that new developments are still to occur in the verification world. We here at Verilab believe our readers can only agree.
