Verilab at DVCon 2014
Tuesday, February 25th, 2014 by Paul MarriottCome and join us at DVCon 2014 in San Jose, CA, from March 3rd - 6th. Several of us from Verilab will be presenting.
Papers:
- TUESDAY March 04
- Session 4 3:00pm - 5:00pm | Oak Ballroom | Paper 4.3 SystemVerilog, Batteries Included: A Programmer’s Utility Library for SystemVerilog by Jonathan Bromley and André Winkelmann
- WEDNESDAY March 05
- Session 9 10:00am - 11:30am | San Jose/Santa Clara Ballroom | Paper 9.1 Advanced UVM Register Modeling - There’s More Than One Way To Skin A Reg
by Mark Litterick and Marcus Harnish - Session 10 3:30pm - 5:00pm | Oak Ballroom | paper 10.1 A Guide to Using Continuous Integration Within the Verification Environment by Gordon McGregor (Nitero Inc.), Jason Sprott, and André Winkelmann
- Session 9 10:00am - 11:30am | San Jose/Santa Clara Ballroom | Paper 9.1 Advanced UVM Register Modeling - There’s More Than One Way To Skin A Reg
Posters:
- TUESDAY March 04 Poster Session 10:30am - 12:00pm | Gateway Foyer
- Poster 1P.10 Demystifying the UVM Configuration Database by Vanessa Cooper and Paul Marriott
- Poster 1P.15 Verification Mind Games - How to Think Like a Verifier by Jeff Montesano and Mark Litterick
Verilab is also sponsoring the best paper and poster awards again this year.
