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Verilab@DVCon 2013 Wrapup

Several folks at Verilab presented material at DVCon 2013. All papers and presentations have now been posted on the Verilab website.

Mark Litterick won the best paper award for his paper entitled SVA Encapsulation in UVM - Enabling Phase and Configuration Aware Assertion
Best Paper and Poster Winners

The slides for Mark’s presentation can be downloaded here: SVA Encapsulation Slides

Paul Marriott presented a poster entitled Run-time Configuration of a Verification Environment - A Novel Use of the OVM/UVM Analysis Pattern and the associated paper can be downloaded here: Run time configuration paper

Mark also presented a poster entitled Pragmatic Verification Reuse in a Vertical World and its associated paper can be downloaded here: Pragmatic reuse paper

As well as winning best paper and presenting a poster, Mark also gave his thoughts on OVM to UVM Migration - or There and Back Again, a Consultant’s Tale which formed part of the tutorial on Lessons from the Trenches: Migrating Legacy Verification Environments to UVM

Peggy Aycinena wrote an interesting piece on Jason Sprott’s participation in the Cadence-sponsored luncheon panel on Best Practices in Verification Planning.

Finally, check out Richard Goering’s writeup of JL Gray’s Industry Leaders Panel: “The Road to 1M Design Starts”

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