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Archive for March, 2013

Silicon Valley SNUG: Sub-cycle Functional Timing Verification Using SystemVerilog Assertions

Tuesday, March 26th, 2013 by Paul Marriott

Verilab’s Anders Nordstrom will be presenting his paper “Sub-cycle Functional Timing Verification using SystemVerilog Assertions” at the Tuesday March 26th session at 10:30 am of SNUG Silicon Valley 2013.

This presentation shows a novel, more complete approach to functional verification of sub-cycle timing using SystemVerilog assertions in an OVM verification environment. This approach found many bugs which otherwise were missed in OVM-only simulations that didn’t include assertions.

This functional sub-cycle timing behaviour includes maintaining fixed delays and phase relationships between inputs and outputs and ensuring there are no glitches on clocks or delayed signals.

SystemVerilog assertions are evaluated on successive occurrences of an event or timing expression. This presents a challenge for sub-cycle timing verification, where there is no obvious reference clock suitable for triggering the assertions. Assertions sample their expressions in the preponed region of the simulation timestep, but the requirements called for sampling both before and after each triggering point. Examples of assertions showing how to overcome this and many other issues will be shown along with recommendations on how to write assertions for functional timing verification.

This paper is complementary to the paper presented by Paul Marriott at DVCon 2013 entitled Run-time Configuration of a Verification Environment - A Novel Use of the OVM/UVM Analysis Pattern. The sub-cycle timing relationships were dynamically varied during simulation and the assertions used were required to check for correctness as the actual relationships varied during the simulation.

Verilab@DVCon 2013 Wrapup

Monday, March 18th, 2013 by Paul Marriott

Several folks at Verilab presented material at DVCon 2013. All papers and presentations have now been posted on the Verilab website.

Mark Litterick won the best paper award for his paper entitled SVA Encapsulation in UVM - Enabling Phase and Configuration Aware Assertion
Best Paper and Poster Winners

The slides for Mark’s presentation can be downloaded here: SVA Encapsulation Slides

Paul Marriott presented a poster entitled Run-time Configuration of a Verification Environment - A Novel Use of the OVM/UVM Analysis Pattern and the associated paper can be downloaded here: Run time configuration paper

Mark also presented a poster entitled Pragmatic Verification Reuse in a Vertical World and its associated paper can be downloaded here: Pragmatic reuse paper

As well as winning best paper and presenting a poster, Mark also gave his thoughts on OVM to UVM Migration - or There and Back Again, a Consultant’s Tale which formed part of the tutorial on Lessons from the Trenches: Migrating Legacy Verification Environments to UVM

Peggy Aycinena wrote an interesting piece on Jason Sprott’s participation in the Cadence-sponsored luncheon panel on Best Practices in Verification Planning.

Finally, check out Richard Goering’s writeup of JL Gray’s Industry Leaders Panel: “The Road to 1M Design Starts”

Verilab at CDNLive Silicon Valley 2013

Friday, March 8th, 2013 by Paul Marriott

Verilab’s Bryan Morris will be presenting his paper “Yes We Kanban: An Introduction to an Agile Management Technique” at the Wednesday March 13th, Session VER204 of CDNLive Silicon Valley 2013.

This presentation provides an overview of the Kanban technique and guidance on how you can start to use it in your team’s ASIC/FPGA development flow.

The key advantages of using Kanban are that it provides a visual overview of what your team is working on, clearly identifies current blocking issues and bottlenecks in your process, and creates opportunities for the team to proactively discuss their processes and resolve any blocking issues.

Work For Verilab