Come join us at DVCon 2013 in San Jose, CA. Several of us from Verilab will be involved in the following activities:
- Monday February 25th, Tutorial Lessons from the Trenches: Migrating Legacy Verification Environments to UVM™ Mark Litterick presenting
- Tuesday February 26th, Poster session Paul Marriott presenting “Run-Time Configuration of a Verification Environment – A Novel Use of the OVM/UVM Analysis Pattern” and Mark Litterick presenting “Pragmatic Verification Reuse in a Vertical World”
- Tuesday February 26th, Paul Marriott is chairing the REGULAR SESSION: Case Studies - I
- Wednesday February 27th “Session 11 - Hardcore UVM-II” Mark Litterick presenting “SVA Encapsulation in UVM - Enabling Phase and Configuration Aware Assertion”
- Wednesday February 27th Luncheon Best Practices in Verification” Jason Sprott, panelist
- Wednesday February 27th JL Gray moderates Industry Leaders Panel: The Road to 1M Design Starts
Verilab is also sponsoring the Best Paper and Poster Award.