Verilab is currently conducting a survey to find out how SystemVerilog/UVM users are, well, using phasing and phase jumping. We would greatly appreciate your feedback! Click on the link below to take the survey.

UVM Runtime Phasing and Phase Jumping Survey

This entry was posted by JL Gray on Tuesday, December 4, 2012 at 5:02 pm and is filed under News, SystemVerilog. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.