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Archive for October, 2012

Thoughts on Verification: A ‘Fresh’ Look at UVM (part 2 of 2)

Tuesday, October 9th, 2012 by Alex Melikian

In Part 2, Verilab consultants Alex Melikian and Vanessa Cooper discuss some of the challenges of learning and adopting the UVM into a new verification environment, or an existing one. They also provide tips and available resources to help one accelerate their ramp-up and adoption process. Part 1 can be viewed here.

Alex Melikian: Let’s talk about the learning curve involved with adopting UVM. These things always imply an initial investment in terms of time. What do you say is the quickest payoff or quickest ROI that someone can gain from using UVM?

Vanessa Cooper: Well, I guess I’ll go back to the reuse issue. You’ve created some code – say, an AHB VIP. Hopefully, the next person who needs an AHB driver doesn’t have to reinvent the wheel because you’ve already created it. If they can pick it up off the shelf and run with it, that’s the quickest payback.

And once you get over the hump of learning the UVM I think productivity increases because everybody’s marching along the same path. You know where the files are. You know what type of files you need to create.

And it’s just a lot easier when someone new comes in, and they know UVM. They don’t have that huge learning curve of “okay now, where would I find my stimulus?” They know exactly where that is. That is another quick payback. But like you said, there is an initial learning curve. I’ll go back to what you said about the registers. I think on my first UVM project the register model was the biggest thorn in my side because it was a tad bit more challenging to learn than just the basic concepts of getting stimulus up and going.

And it took awhile of really stepping through the library, understanding what was going on, and how the register could be used as a scoreboard, how to do checking before I got it up and working correctly. Now, once that’s done, doing it again is simpler.
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