In part 3, JL and Alex discuss some of the methodologies, outside of, but complimentary to HVL technologies, such as continuous integration. Typical mistakes and growing pains of adopting HVL methodologies are also reviewed. Finally, JL discusses about his verification blog, along with the various discussions and debates it has generated.

Alex Melikian: Sometimes the verification work that we do isn’t just about coding and writing requirements, test benches and test cases, but it involves usually a lot more than that.  For example, setting up a compute farm. Very often, verification engineers are involved with putting the compute farms together or at least giving some feedback into how it should be assembled. The setup of an adequate revision control or other EDA related elements are other examples.  Is there any particular challenge you took on that was related to verification work, where a client didn’t expect you to take on but recognized the importance of it once completed?

JL Gray: Well, one of the things in that area is the introduction of continuous integration techniques. Backing up, I think the major problems that exist on projects, regardless of whether they are using constrained random verification or not, are the project planning and the methodologies employed to carry the planning out. For example, the division of labor between design and verification engineers is frequently sub-optimal. And engineers often make decisions for the purpose of guarding their turf that do not support the success of the project.  Another issue would be design engineers who make decisions without taking into account the impacts or consequences on verification. These are, I think, the biggest problems that are faced – nothing to do with whether you use constrained random test benches or not.

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In part 2 of 3 of this conversation, JL and Alex talk over risks/reward involved with adopting an HVL workflow, as well as the diverging perspectives from management and engineers in a company. Also, they discuss the state of HVL technologies today and what might evolve from it next. Part 1 can be viewed here.

Alex Melikian: You bring up another hidden risk of not doing verification, negative cases that were unchecked in the design. Which once again comes back to our initial statement that unfortunately it sometimes takes a big and costly failure for some firms to realize that they do need verification, rather than taking a proactive stance and adopting it before the big costly failure happens.

JL Gray: But there is an interesting tradeoff though. I think there’s a big disconnect between the way that staff engineers view projects and the way that the senior management views projects. I often find that there’s a miscommunication that occurs there. The staff engineers are looking up and saying “if we would only just spend some money on this it would save us from so much pain” or we wouldn’t have to spend on so many re-spins on a chip. What are these guys in the senior management thinking? – They’re fools they don’t know what they’re doing.

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Verilab is pleased to introduce “Conversations About Verification”, a monthly publication featuring a discussion on VLSI verification topics. In this inaugural edition, Verilab consultant Alex Melikian discusses first experiences and adoptions of modern verification technologies with JL Gray, Vice President and General Manager, North America of Verilab.

In part 1, JL and Alex discuss about their first experiences involving advanced verification languages and methodologies. They also discuss why and how ASIC/FPGA development centers adopt and integrate Hardware Verification Languages (HVL) and related methodologies into their workflow. In addition, they also discuss some of the impediments as to why others hesitate to make the adoption.

Alex Melikian: Hi JL, thanks for participating in our inaugural conversation. Before we get things started maybe we should introduce ourselves to our readers. Since you’re the guest, go ahead first.

JL Gray: Sure. I’m JL at Verilab, I head up the North American operations. I also work with clients on coaching and consulting in the areas of verification planning, SystemVerilog, UVM, and other related types of verification activities. I’m also involved with the Accellera Verification IP Technical Subcommittee as a representative for Verilab. People can read up more about me through my bio.

AM: OK. I myself have been doing verification for about ten years now. I started out with Specman and was in the FPGA/ASIC department of a telecom company. The department was investigating new verification languages that were emerging and they assigned me on a team to do some research with Specman. That was my first taste of verification. It wasn’t like I had planned to specialize in verification when I graduated form university, the EDA industry had just started to produce concepts like functional coverage and the paradigm of verification into ASIC/FPGA development. But I found it to be a really powerful concept. It was a good balance between object-oriented software programming and low level HDL design. I found that really cool and I stuck with it. I have since moved on to learning and applying SystemC and SystemVerilog as well. What was your first experience with verification?
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