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Verilab at DAC, SNUG Technical Committee Award

With the 49th DAC almost upon us, design and verification engineers will inevitably be thinking of the latest and greatest tools on offer from the EDA vendors. Despite complaints of ever increasing complexity being a problem, somehow the tools we’ve been using for the past several decades have been good enough to allow Moore’s Law to continue unabated, with 22nm technology being the latest production point on this exponential curve. Verilab will be there, as usual, to cover this important event and our VP and blogger-in-chief, JL Gray will be covering this over on Cool Verification.

As much as new shiny tools are interesting, sometimes it’s interesting to focus on some more mundane aspect of verification. Often verifiers are faced with what appears to be a simple problem, but which isn’t implemented in any vendor-neutral methodology. It’s always tempting to use tool-specific code, but fewer companies have the ability to restrict themselves to only one vendor over the lifetime of a product and its subsequent revisions. This is where methodologies such as the UVM are particularly useful. However, as much as they are touted as the solution to today’s verification problem, they often are missing some features which make a verifier’s job easier.

One such example is the ability to monitor value changes on arbitrary signals in the DUT without having to have a lot of hard-coded cross-module references. Such references make re-usability difficult, either when a block is reused in a top-level environment or in a completely different environment altogether. It would be nice if such references could be simply specified as strings and then advantage could be taken of the UVM’s configuration database to set and appropriate string for the use-case in question. However, such a facility is not part of the UVM right now.

Fortunately, Verilab’s Jonathan Bromley was motivated enough, when faced with this problem in a real project, to come up with a novel package that uses the SystemVerilog VPI/DPI to neatly provide a solution that works in the three major simulators that support the UVM. Jonathan¬† presented his paper on this at SNUG Munich on May 23rd and at SNUG UK on May 24th. His paper received the Technical Committee’s “Best Paper Award”.

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