Mark Litterick’s OCP-IP December 2008 newsletter article demonstrates how two key aspects of OCP – profiles and transactions — were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems.

The article uses the Verilab OCP uVC as an example. This uVC is a mixed-language OCP compliant verification component that supports a major subset of Open Core Protocol Specification 2.2. The OCP uVC is implemented using SystemVerilog and e verification languages and complies with both the Open Verification Methodology (OVM) and e Reuse Methodology (eRM). The verification component can be used in SystemVerilog only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular eVC.

The OCP-IP article can be downloaded here

The full whitepaper can be downloaded here

This entry was posted by Jason Sprott on Wednesday, January 7, 2009 at 6:18 am and is filed under Info, News, SystemVerilog. You can follow any responses to this entry through the RSS 2.0 feed. Both comments and pings are currently closed.