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DFT Digest: Secure Design-For-Test

Folks interested in DFT would do well to head over to DFT Digest. In his latest post, John Ford ponders about the potential for hackers to learn information about the inner workings of a device via a side channel attack using scan chains. The topic reminds me of a presentation I attended at this year’s DATE conference in Nice. The presenter was discussing security issues and described how she wrapped her passport in aluminum foil to prevent would-be hackers from scanning info out of the embedded RFID chip.

Separately, John is compiling a list of DFT related links. If you’ve got some good ones to share head on over to his DFT Bookcase and or his DFT Forum and let him know!

One Response to “DFT Digest: Secure Design-For-Test”

  1. John Says:

    Thanks for the hat tip JL - much appreciated. I’ll surely return the favor.

    Having done a smidge of verification in my time, I find the Verilab (and CoolVerification) content interesting - and what’s most interesting to me is that fact that it’s grown so fast into something that is beyond my hardware-oriented aptitudes. ‘e’, SystemVerilog: OO is something I never got in school! I guess it’s best left to the experts, like Verilab!

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