Power-Aware Verification at DAC
Power-aware design and verification is a hot topic this year at DAC. I attended the “Design and Verification of Low Power ICs” workshop on Sunday, which mainly focused on Version 1.0 of Accellera’s Unified Power Format (UPF) Standard. The thing I was particularly interested in was how (if at all) UPF could help us functionally verify power-aware logic at the RTL level. If bugs can be found in power implementation at the RTL level, it is far more cost effective and practical than trying to find them at gate-level, or later. The workshop included of a number of presentations from different EDA vendors illustrating how UPF can be used to do just that.
Until recently power has been treated as a secondary concern in chip designs, where implementation and verification of power-aware circuitry is done quite late in the design cycle, and certainly not at RTL level.
This is mainly because power-aware information is typically not implemented in the HDL logic itself, as that would tie the logic specification to a particular power implementation, and some power-aware information cannot be specified in HDL. UPF aims to provide a mechanism where power can be considered as early as the RTL phase, without the need to modify the HDL code itself.
Gary Delp (LSI) gave a pretty good overview of a typical UPF design flow, showing how an HDL design could be augmented with power specific implementation information, in the form of separate “Power Source Files”. These files are not part of the HDL design, but can be read in by the tools at the same time as the design. The tools can then automatically understand how to treat the parts of the design relevant to power for simulation etc. This seems like a good solution as the HDL designs could be used on many applications, each with different power considerations.
Mike Keating (Synopsys) then broke down a generic power gating design into its different concerns: power domains, the selection and control of these domains, power switches, retention registers, boundary isolation and level shifting elements. For each aspect he gave examples of the UPF commands used to describe the behaviour of power functionality. Mike showed how the commands create the relevant domains and elements, and also connect them up to the design.
Stephen Bailey (Mentor Graphics) presented the verification semantics and capabilities of UPF. Using an interleaver example, he described how UPF can be used to specify power down/up behaviour during simulation, e.g. the state wires are driven to for logic that is powered down, retention register state, or isolated outputs. He also briefly described the VHDL and SystemVerilog packages defined by UPF for driving and reading power specific supply nets. These packages can be used for modelling specific power functionality, e.g. a power switch. Stephen also described two options for verifying save and restore protocols:
- Boolean mutex assertions built into the set_retention_control command, for simple scenarios.
- Mapping retention behaviour onto a model, for more complex scenarios.
UPF seems to provide us with a good way to start power-aware verification as early as the RTL phase. The UPF standard was adopted quickly by Synopsys, Mentor, and Magma (among others). However, Cadence is backing another solution called the Common Power Format (CPF), now a Silicon Integration Initiative (Si2) specification (not standard), which addresses the problem in a similar way. In fact CPF got a head start on UPF, but some people didn’t think CPF was open enough, so they backed UPF instead.
This is definitely an area of verification to watch. Things are starting to get quite interesting and it’s possible to do RTL simulations today on power-aware designs. It is a bit different to the usual RTL level modelling and simulation we’re used to, but in our complex low power SoCs early verification of power-aware designs is going to become more and more critical.
Jason
