I was feeling a bit jet lagged today at DAC – nothing to do with the wine the evening before – so I decided to visit the Oxygen Party Bar installed at the Mentor Graphics booth. The friendly “bar staff” were only too happy to advise me that a 10 minute shot of the 90 percent concentration of aroma-scented oxygen, would give me “immediate relief”.
We made it through our first day at DAC 2007. It has been several years since I last visited DAC, but it did not seem to be as well attended this year. Aside from that, I saw a lot of new companies, many of which are start-ups trying to find their place in the EDA world. It is mind boggling to see how many companies are evolving to address the many complex design and verification tasks.
(more…)
Power-aware design and verification is a hot topic this year at DAC. I attended the “Design and Verification of Low Power ICs” workshop on Sunday, which mainly focused on Version 1.0 of Accellera’s Unified Power Format (UPF) Standard. The thing I was particularly interested in was how (if at all) UPF could help us functionally verify power-aware logic at the RTL level. If bugs can be found in power implementation at the RTL level, it is far more cost effective and practical than trying to find them at gate-level, or later. The workshop included of a number of presentations from different EDA vendors illustrating how UPF can be used to do just that.
(more…)
Today I had the opportunity to meet with Sean Smith, Chief Verification Architect, and Tim Cook, Staff Software Engineer at Denali. Sean and Tim were kind enough to spend an hour and a half discussing SystemRDL, Blueprint, and PureSpec SystemRDL with me. For those of you unfamiliar with these products, they cn be summarized as follows:
Here is a quick FYI for those of you who may have noticed a bit of a language difference between some of the posts on the blog so far. Verilab has offices in the UK, Germany, and US. As such, the articles on the blog and website may end up alternating between US and UK English. Of course, we all know which one makes the most sense, but to ward off an international incident I’ll concede that either one is grammatically correct, and leave it at that… for now.
By the way, along with the new website we’ve created a new Careers section with a handy form to allow you to submit your resume. We’re actively looking for highly talented individuals to join us. If you’re eligible to work in the US or European Union, please let us know if you’re interested!
JL
I had one of those “Doh! Why didn’t I think of that?” moments at the Mentor booth today. Mentor have a new tool [1] in the pipe called InFact which solves a problem in stimuli generation that you might not even have realised you had [2]. Once it’s pointed out to you, you might start wondering why you put up with it for so long.
Have you ever run a regression and found it took ages to hit those last few functional coverage points? For example, you fully define your AHB transaction, but you never seem to hit that weird WRAP8 BUSY 16bit OPCODE scenario. No matter how many tests you run, it just never seems to get hit, although you’ve hit some other scenarios a million times.
That seems like a bit of a waste of time.
(more…)
Yep - that’s right. Gary Smith announced it this morning at DAC. Now it might come as a surprise to those of us who are working in the area of hardware verification, but apparently it’s true. It certainly came as a surprise to me, and to a friend of mine who’s the manager of a hardware team, but perhaps we just have a different interpretation of “under control”. Those of us deep in the verification trenches might say a lot of things about the state of verification today, but I’m not sure “under control” would be one of them 
(more…)
