DAC Day 1
We made it through our first day at DAC 2007. It has been several years since I last visited DAC, but it did not seem to be as well attended this year. Aside from that, I saw a lot of new companies, many of which are start-ups trying to find their place in the EDA world. It is mind boggling to see how many companies are evolving to address the many complex design and verification tasks.
Mentor Breakfast – Jason and I attended the Mentor Vanguard Partners breakfast. They had four speakers in the form of Robert Hum, Jan Johnson, Keith Gover, Dennis Brophy( Dennis spoke in place of Steve Bailey on PowerAware). The PowerAware presentation was pretty interesting and was in line with the theme of DAC44. I think Jason has written something in depth on the PowerAware presesentations.
They also presented some impressive numbers on the activity around System Verilog:
- 250 SV customers
- 4000 downloads of AVM
- 800 members in the SVUG
It would have been interesting to know how many of those SV users are actually still using it and how many of them have gone back to their original methodology or to another approach other than SV – just wondering.
Davie and I attended the presentation by Mentor on the Algorithmic Testbench Generation. It seemed to me that the major benefit of this approach was to allow you to generate constrained random test sequences and insure that they never generated duplicate sequences. This could save many cycles over a long run of constrained sequences.
Later in the day JL and I sat through a demo on the Axiom simulator. It was claimed that the simulator supported Verilog, VHDL, Vera, SV, and SystemC. When JL asked them about what was not supported in SV, they said it was still under development. It was not clear whether they actually support SV or not at this time.
Davie, JL, and I also sat through a very good demo by NEC on their C-based Cyber-Work-Bench. Their entire flow for both design and verification is based on C and includes all of the normal tools found in a conventional flow including synthesis, equivalence checkers and timing closure tools. They use this flow across all NEC and have taped out many hundreds of chips using the flow. JL and Davie asked many detailed questions about the tools and flow and the NEC guy did a good job of answering the questions. Though I believe they have created the kind of cohesive flow all of the EDA companies talk about, it is going to be a hard cell to convince a verilog/vhdl entrenched design community to use C for all their development. But I think it solves many of the problems of evaluating complex architectures for function and performance with the ability to go directly from the architecture models to the silicon. It also eliminates a huge EDA budget.
