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Carbon Design Maps RTL to C

After the keynote on Tuesday I had the opportunity to meet Soha Hassoun, an Associate Professor of Computer Science at Tufts University, while snapping a photo of Steven Levitan (DAC conference chair). Among other things, Soha is involved with a company called Carbon Design Systems. Now, as it turns out I’ve been bombarded with emails from Georgia Marszalek from ValleyPR about Carbon, but for some reason I never fully grasped the value of the company’s product after reading an email description. Based on the additional recommendation from Soha I decided to take a look.

Thursday morning I went by the Carbon booth and spoke with Elizabeth Abraham, VP, Consulting Services and Product Marketing. She gave me an overview of Carbon’s Virtual System Prototype (VSP) software. VSP converts “Verilog, VHDL, and mixed language RTL designs into an ultra-fast, cycle-accurate virtual prototype.” Basically, RTL is converted to high level C software model which can run 10-100x faster than the original design, according to Elizabeth. The other cool feature of Carbon’s product is the ability to debug hardware and software side by side, as bugs tracked down in the generated C code can be mapped back to the original hardware implementation.

I asked Elizabeth how VSP compared with solutions such as the Cadence ISX, which can provide coverage metrics and constrained random testing for embedded software. Based on my understanding of the tools, it appears VSP is focused on verifying the full system hardware/software solution, whereas ISX is focused on testing the interface layer between the system software and hardware (i.e. not the entire software solution). The other difference is that VSP should dramatically speed up simulations whereas ISX would not unless it was paired with a Palladium hardware accelleration box.

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