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Averant’s Larry Lapides on Formal Verification

Thursday morning at DAC I had the opportunity to speak with Larry Lapides, VP of Worldwide Sales for Averant about formal verification and Averant’s formal verification product Solidify.  Averant’s formal tools compete with those from Jasper, OneSpin, Cadence, and Synopsys, among others. 

I asked Larry if he could share some of the most common reasons people decide to use formal tools.  According to Larry, people are using far more advanced techniques with dynamic simulation these days, but they are still on the lookout for ways to improve their ability to achieve first pass success.  This is especially true as reuse becomes a bigger issue, both between companies and between projects within a company.  Dynamic verification is not likely to find bugs that can come up when a module is used in another system.  Formal verification compliments dynamic simulation and can help find issues that wouldn’t have otherwise been considered during the initial verification effort.

Larry pointed out that the longer it takes to find a bug, the more expensive it is to fix.  Formal tools used in conjunction with dynamic simulation can help users catch bugs earlier in design cycle. 

The main thing I took away from my discussion with Larry was that the use of formal tools doesn’t require users to abandon dynamic simulation techniques.  Additionally, formal works best on modules of less than 1M gates.  It is especially strong when dealing with control path logic, including deadlock/livelock checks.  Simulation, on the other hand, is better at handling data flow, though formal can be used as well.  Mission/safety critical applications also benefit from the added completeness provided by formal tools. 

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