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Synopsys SystemVerilog Support

According to a helpful representative at the Synopsys booth this afternoon, VCS supports 99% of the SystemVerilog Testbench features. Which 99%? I’m aware it doesn’t support parameterized classes or the shuffle() method for arrays. I’m sure there must be more features as well. Also, a heads up. While browsing through the VCS documentation recently I discovered documentation on AOP extensions for SystemVerilog built into VCS. I haven’t tried it out yet to see if it works. However, as with Vera, the AOP support is nothing like the “when inheritance” found in Specman/e. When Inheritance allows fields, methods, and additions to methods to be added into an instance of a class only when a given field has been randomly set to a specified value.

Also useful to know? The 2006.06-12 release of VCS fixes several bugs in the graphical debugger (DVE) related to SystemVerilog.

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