JL Gray and Gordon McGregor’s DVCon 2012 paper on Continuous Integration using Jenkins has been posted in the “Papers and Presentations” section of the Verilab website.

We’re hiring in the UK. Check out our LinkedIn job advert for details.

We’re hiring in Austin. Check out our LinkedIn job advert for details.

Come join us at DVCon 2012 in San Jose, CA. Several of us from Verilab will be involved in the following activities:

• Monday, February 27 - UVM: Ready, Set, Deploy. Vanessa Cooper presenting.
• Tuesday, February 28 - Industry Leaders Panel: The Resurgence of Chip Design. Moderator: JL Gray
• Tuesday, February 28 - A 30-Minute Project Makeover Using Continuous Integration. JL Gray and Gordon McGregor

Verilab will also be sponsoring this year’s best paper award. We look forward to seeing you there!

Rumor has it we’ve been staffing a team in Canada with engineers in Ottawa and Montreal. If you’re interested in joining go ahead and submit an application today!

Verilab’s award-winning paper entitled “Using the New Features in VMM 1.1 for Multi-Stream Scenarios” is now available for download from the Verilab website. Please let us know if you have any questions!

Verilab have added their OCP uVC verification component to the OCP-IP Library.

The Verilab OCP uVC is a mixed language verification component for the Open Core Protocol (OCP) implemented using SystemVerilog and e verification languages. It can be used as an Open Verification Methodology (OVM) Verification Component (OVC) in SystemVerilog-only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular e Verification Component (eVC).

The datasheet for the OCP uVC can be downloaded here

Mark Litterick’s “Architecting the OCP uVC verification component” article written about in a previous blog has also been picked up by EDA Designline

Mark Litterick’s OCP-IP December 2008 newsletter article demonstrates how two key aspects of OCP – profiles and transactions — were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems.

The article uses the Verilab OCP uVC as an example. This uVC is a mixed-language OCP compliant verification component that supports a major subset of Open Core Protocol Specification 2.2. The OCP uVC is implemented using SystemVerilog and e verification languages and complies with both the Open Verification Methodology (OVM) and e Reuse Methodology (eRM). The verification component can be used in SystemVerilog only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular eVC.

The OCP-IP article can be downloaded here

The full whitepaper can be downloaded here

Just a quick FYI… both David Robinson and I have posted our DAC presentations on Verification Planning and SystemVerilog Interoperability on the Verilab website. Please check them out and let us know if you have any questions or comments!