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DVCon 2017: “SV Jinxed Half My Career” Panel Preview

February 7, 2017 by Alex Melikian

Verilab is proud to have senior consultant Jonathan Bromley host the “SystemVerilog Jinxed Half My Career” panel at DVCon 2017, on Wednesday March 1st. Jonathan continues to serve on the SystemVerilog IEEE committee and is the author of numerous papers, including the recently published “Slicing Through the UVM’s Red Tape”. We took a moment with Jonathan to preview what this panel will cover and what those planning or thinking of attending should expect.


The title is “SystemVerilog Jinxed Half My Career : Where do we go from here”, which signals this panel will focus on areas of improvement. What are those areas of frustration in SystemVerilog you feel need improvement?

It would be easy to give a “where do I start?” response, and it’s not difficult to come up with a laundry list of desirable SystemVerilog improvements and nit-picky complaints. But this is DVCon, and our very knowledgeable and sophisticated audience deserves better. We have five extraordinarily experienced panelists and I hope we can venture beyond details of the languages and tools we have today, and think creatively about what we can and should hope for in the mid-term future. Many languages have been used successfully to create advanced testbenches - ‘e’, C++, Python, Vlang - but there’s no question that SystemVerilog remains dominant. Why is that? What sort of code will verification engineers be writing in five, ten years’ time?
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DVCon Europe 2016: Slicing Through the UVM’s Red Tape - A Frustrated User’s Survival Guide

October 18, 2016 by Paul Marriott

Jonathan Bromley will be presenting a paper on Thursday 20th, in session 1 (3:15-4:30PM), examining some of the challenges and frustrations for novice and intermediate-level users of the UVM on real projects.

This paper looks at typical examples of such challenges, and offers solutions that respect fundamental aims of the UVM: consistency, reusability, and expressive power.

If you’ve struggled with the integration of directed tests, external models into the sequences mechanism, reconciling the abstract and the untimed nature of sequences with the need for precise control over stimulus timing, proper use of the configuration database, or working with a parameterized device-under-test, this presentation might be for you.

A full description of the tutorial is detailed in the DVCon Europe 2016 conference program

DVCon Europe 2016: Formal Verification - Too Good To Miss

October 17, 2016 by Paul Marriott

Jonathan Bromley and Jason Sprott will be delivering a tutorial on Wednesday 19th October 10:00-11:30AM at DVCon Europe 2016 in Munich.

We find that getting started on formal verification can be a challenge. It’s different to traditional simulation, with some unfamiliar concepts. However, for the right kind of problem, it’s just too good to miss out on due to the lack of experience. This tutorial aims to address that initial lack of confidence and basic knowledge, helping engineers to get started on real project work using formal verification. We’ll be using a small case study to take attendees through the lifecycle of a formal verification project for a block-level RTL design.

A full description of the tutorial is detailed in the DVCon Europe 2016 conference program

Verilab Presentations From SNUG Austin

October 13, 2016 by Paul Marriott

Jeff Montesano and Jeff Vance presented their paper entitled “Configuring a Date with a Model – A Guide to Configuration Objects and Register Models” at SNUG Austin this past September 2016.

The full paper and presentation slide can be downloaded from our resources section: snug2016model.

Jonathan Bromley, Mark Litterick, and Vanessa Cooper’s paper entitled “Effective SystemVerilog Functional Coverage: design and coding recommendations” can also be downloaded from our resources section: snug2016cover. Unfortunately, Vanessa was unable to present this due to sickness, though this paper did win the Technical Committee Honourable Mention Award at SNUG2016UK.

Thanks to all who attended!

All of our papers and presentations can be downloaded from our resources page’s papers-and-presentations section.

Verilab at SNUG Austin 2016

September 26, 2016 by Alex Melikian

We’re proud to announce Verilab consultants Jeff Montesano, Jeff Vance and Vanessa Cooper will be presenting at SNUG Austin 2016 this Thursday September 29th.

Jeff Montesano and Jeff Vance will present “Configuring a Date with a Model – A Guide to Configuration Objects and Register Models” in the morning session. In addition, as conference technical chair, J. Montesano will have the pleasure to give a short address and introduce the morning keynote speakers.

Vanessa Cooper will present “Effective SystemVerilog Functional Coverage: Design and Coding Recommendations” in the afternoon session.

For more information on times and events consult the schedule, or download the “SNUG Austin” mobile app.

We look forward to seeing you there and hear what you have to say about verification.

“Formal Verification - Getting Started with Confidence” Webinar

June 9, 2016 by Alex Melikian

Here at Verilab, we’re seeing an increase in formal verification being used on client projects. The tools have come a long way, especially with formal “Apps” that focus on some specific activities, increasing automation for formal tasks.

Today’s formal tools are a serious alternative to simulation for many functional verification tasks. A strong understanding of the terminology, techniques and general tool capabilities is key for a successful adoption. Although the formal tools look different to one another and have different strengths and weaknesses, the underlying techniques are the same. The domain terminology used is consistent and there are standard input languages. Most of what you’ll need to learn applies to tools across the board.

Interested in dipping a toe in the water?

We’ve partnered with Doulos to deliver a FREE webinar “Formal Verification - Getting Started with Confidence”, an introductory session highlighting some key concepts. No experience with formal verification is required.

The webinar will be presented on June 17th, 2016. For more details and registration click here:
Formal Verification - Getting Started with Confidence


DVCon 2016 Best Paper / Poster Awards

March 3, 2016 by Paul Marriott

Everyone at Verilab would like to congratulate the winners of the 2016 Best Paper and Poster awards which we were proud to sponsor.

BEST PAPER
1st Place

8.2: Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012
Speaker: Eldon G. Nelson - Intel Corp.

2nd Place

5.1: SystemVerilog Interface Classes - More Useful Than You Thought
Speaker: Stan Sokorac - ARM, Inc.

3rd Place

9.3: Functional Coverage Collection for Analog Circuits – Enabling Seamless Collaboration Between Design and Verification
Speaker:Zhipeng Ye - Texas Instruments, Inc.
Authors:Zhipeng Ye - Texas Instruments, Inc.
Honghuang Lin - Texas Instruments, Inc.
Asad Khan - Texas Instruments, Inc

BEST POSTER
1st Place

4P.32 Marrying Simulation and Formal Made Easier!
Speaker:Lun Li - Samsung Austin R&D Center
Authors:Lun Li - Samsung Austin R&D Center
Durga Rangarajan - Samsung Austin R&D Center
Christopher Starr - Samsung Austin R&D Center
James Greene - Samsung Austin R&D Center
Nitin Mhaske - Synopsys, Inc.

2nd Place

4P.22 Improving the UVM Register Model: Adding Product Feature Based API for Easier Test Programming
Speaker:Krishnan Balakrishnan - Analog Devices, Inc.
Authors:Krishnan Balakrishnan - Analog Devices, Inc.
Courtney Fricano - Analog Devices, Inc.
Kaushal M. Modi - Analog Devices, Inc.

3rd Place

4P.14 How Do You Verify Your Verification Components
Speakers:Neil Johnson - XtremeEDA Corp.
Joshua W. Rensch - Superion Technology

Authors:Joshua W. Rensch - Superion Technology
Neil Johnson - XtremeEDA Corp.

Verilab at DVCon 2016

February 25, 2016 by Paul Marriott

Come and join us at DVCon 2016 in San Jose, CA, from February 29th - March 3rd, 2016.

Verilab’s Vanessa Cooper is this year’s Panel Chair and this is what she has to say about the line-up for 2016:

We had a number of excellent panel submissions to consider this year, and selected two that I think are of particular importance and address issues our audience is concerned with right now. Both panels will be held on Wednesday, March 2.

The first panel, “Redefining ESL” will be moderated by Brian Bailey. They will attempt to define ESL verification, from tools to flows. As they discuss, “How or when can all the disparate pieces be brought together, or is that even necessary?” there will be plenty of angles to consider.

The second panel, “Emulation + Static Verification Will Replace Simulation” will be moderated by Jim Hogan of Vista Ventures. The panel will discuss where it sees the verification paradigm of the future and where it leaves RTL simulation. It promises to be a lively discussion!

Bringing together two distinct groups of experts, I think attendees will be pleased by the different discussions and varying points of view offered by both of panels. We look forward to seeing you at DVCon U.S.!

Mark Litterick will be presenting his paper, entitled “Full Flow Clock Domain Crossing - From Source to Si”,  in the Design and Modeling Approaches session at 9am on Tuesday March 1st. This is the paper’s abstract:

Functional verification of clock domain crossing (CDC) signals is normally concluded on a register- transfer level (RTL) representation of the design. However, physical design implementation during the back-end pre-silicon stages of the flow, which turns the RTL into an optimized gate-level representation, can interfere with synchronizer operation or compromise the effectiveness of the synchronizers by eroding the mean time between failures (MTBF). This paper aims to enhance cross-discipline awareness by providing a comprehensive explanation of the problems that can arise in the physical implementation stages including a detailed analysis of timing intent for common synchronizer circuits.

Thoughts On Verification: Keeping Up With Specman (part 2 of 2)

February 22, 2016 by Alex Melikian

In Part 2, Alex and Thorsten continue discussing the latest developments with Specman and the ‘e’ language, along with practical use cases. They focus on coverage driven distribution and how anonymous methods can be applied. Part 1 of the conversation can be viewed here.


Alex Melikian: Okay. Moving on to another topic, let’s talk about something introduced at a recent conference covering Specman: the notion of coverage driven distribution. This has been something that’s been in the works for some time, now. It’s not 100% complete yet, but it looks like Specman features supporting coverage driven distribution are becoming piece by piece available. Before we get into that, once again for the readers that are not familiar with it, can you explain what are the concepts behind coverage driven distribution?


Thorsten Dworzak: Yes. So the typical problem for coverage closure in the projects we are usually working on as verification engineers is that you have this S curve of coverage completeness. You start slowly and then you easily ramp up your coverage numbers or your metrics to a high number like 80/90 percent.

And then in the upper part of the S curve it slows down because you have corner cases that are hard to reach, etc., etc. And it takes a lot of time to fill the gaps in the coverage over the last mile. So people at Specman have done some thinking about it. And of course one of the ideas that has been around in the community for some time is that you look at your coverage results and feed them back into the constraints solver.

But this is a different approach. Here you look at the actual coverage implementation and derive your constraints from this, or you guide your constraints from your actual coverage implementation. So to give an example, you have an AXI bus and an AXI transaction comprising of an address, a strobe value, direction, and so on. And in your transaction based coverage you have defined certain corner cases like hitting address zero, address 0xFFFF and so on. And whenever Specman is able to link this coverage group to the actual transaction, which is not easy and I’ll come to that later – then it can guide the constraints solver to create higher probability for these corner cases in the stimulus.
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Thoughts On Verification: Keeping Up With Specman (part 1 of 2)

February 4, 2016 by Alex Melikian

In this edition of “Thoughts On Verification”, Verilab consultant Alex Melikian interviews fellow consultant Thorsten Dworzak over recently released features from Specman and the ‘e’ language. With nearly 15 years verification experience, Thorsten has worked extensively with Specman and ‘e’, as well as regularly participating in conferences covering related subjects tools.

In Part 1, Alex goes over new features from Specman as Thorsten weighs-in on what he feels are the most practical according to his experience. In addition they discuss in detail the language and tool’s support for employing “Test Driven Development” methodology.

Alex Melikian: Hi everyone, once again, Alex Melikian here back for another edition of Thoughts on Verification. We’ve covered many topics on these blogs but have yet to do one focusing on Specman and the ‘e’ language. To do so, I’m very pleased to have a long time Verilab colleague of mine, Thorsten Dworzak with me. Like me, Thorsten has been in the verification business for some time now, and is one of the most experienced users of Specman I personally know. Actually, Thorsten, I should let you introduce yourself to our readers. Talk about how you got into verification, what your background is and how long you’ve been working with Specman and ‘e’.


Thorsten Dworzak: Yes, so first of all Alex, thank you for this opportunity. I’m a big fan of your series and okay, let’s dive right into it. I’ve been doing design and verification of ASICs since 1997 in the industrial, embedded, consumer, and automotive industry - so almost all there is.

And I’ve always been doing, like, both; design and verification, say 50 percent of each and started using Specman around 2000. That was even before they had a reuse methodology and they didn’t even have things like sequences, drives, and monitors. Later on I was still active in both domains but then I saw that the design domain was getting less exciting. Basically plugging IPs together, somebody writing a bit of glue logic and the bulk of it is being generated by in-house or commercial tools.

So I decided to move to verification full time and then I had the great opportunity to join Verilab in 2010.


AM: Of course your scope of knowledge in verification extends to areas outside of Specman. But since you’ve been working with it since the year 2000, I’m happy to have a chance to cover subjects focusing on it with you. That year is particular for me as I started working with Specman around that time, and I’ve felt that was the era where it and other constrained-random, coverage driven verification tools really took off.

It’s been a couple of years since I’ve last worked with Specman. However, you’ve been following it very closely. What are some of the recent developments in Specman that you think users of this tool and the ‘e’ language should be paying attention to?
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