Read-Evaluate-Start-Sequence-Loop (RESSL - pronounced "wrestle") is inspired by the Read-Evaluate-Print-Loop (REPL) found in Lisp and Python. The REPL in these languages encourage a rapid, iterative and interactive development process allowing the user to easily develop and test new sequences with a minimum of overhead. In the context of ASIC verification, RESSL enables the iterative development and debug of UVM sequences. Similar to the Lisp REPL, it includes four phases:

• Read: A simple interpreter allowing the user to input commands via STDIN.
• Evaluate: The evaluator takes those commands and executes them. These commands include among others, the ability to clone, alter parameters and start sequences.
• Start-Sequence: The system starts the sequence (and any sub-sequences) defined.
• Loop: Clean up and return back to the Read phase.

This paper provides details on the usage model, implementation and future work planned for the RESSL. A specially modified version of UVM-1.2 (with introspection) is required to use ressl and is supplied. You will need to also download svlib

RESSL code download

Modified UVM-1.2 (with introspection) download

( Bryan Morris , Jeff McNeal )