This tutorial provides intermediate and advanced users of the Universal Verification Methodology (UVM) with some more in-depth material on key topics that will help take their understanding and effectiveness to the next level. It is aimed at engineers with a good understanding of SystemVerilog and practical experience in either OVM or UVM.

fter a very brief introduction to UVM in order set the scene and put the other topics into context, the tutorial takes a more detailed look at four topics that have been selected based on Verilab's combined experience implementing pragmatic UVM solutions on many projects at different clients:

• Demystifying the UVM Configuration Database

• Behind the Scenes of the UVM Factory

• Effective Stimulus & Sequence Hierarchies

• Advanced UVM Register Modeling & Performance

( Jason Sprott , Mark Litterick , Jonathan Bromley , Vanessa Cooper )